MuCCRA chips: Configurable dynamically-reconfigurable processors

Hideharu Amano; Yohei Hasegawa; Satoshi Tsutsumi; Takuro Nakamura; Takashi Nishimura; Vasutan Tanbunheng; Aepu Parimala; Toru Sano; Masaru Kato

doi:10.1109/ASSCC.2007.4425711

MuCCRA chips: Configurable dynamically-reconfigurable processors

Hideharu Amano, Yohei Hasegawa, Satoshi Tsutsumi, Takuro Nakamura, Takashi Nishimura, Vasutan Tanbunheng, Aepu Parimala, Toru Sano, Masaru Kato

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

43 Citations (Scopus)

Abstract

Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in System-On-Chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application. That is, DRPAs should be configurable for target SoCs and applications. MuCCRA is a project for developing a DRPA generator which can generate RTL model, testing environment and programming environment for various types of DRPAs just by selecting the specific parameters. Here, two prototype chips MuCCRA-1 and MuCCRA-2 developed in the project are introduced and evaluated. MuCCRA-1 was implemented with Rohm's 0.18um CMOS process mainly for multi-media applications, while MuCCRA-2 with ASPLA's 90nm CMOS process was designed focusing on area optimization used as a cost-effective IP in multi-core SoCs.

Original language	English
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages	384-387
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425711
Publication status	Published - 2007 Dec 1
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: 2007 Nov 12 → 2007 Nov 14

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/Territory	Korea, Republic of
City	Jeju
Period	07/11/12 → 07/11/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2007.4425711

Cite this

Amano, H., Hasegawa, Y., Tsutsumi, S., Nakamura, T., Nishimura, T., Tanbunheng, V., Parimala, A., Sano, T., & Kato, M. (2007). MuCCRA chips: Configurable dynamically-reconfigurable processors. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 384-387). [4425711] (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425711

Amano, H, Hasegawa, Y, Tsutsumi, S, Nakamura, T, Nishimura, T, Tanbunheng, V, Parimala, A, Sano, T & Kato, M 2007, MuCCRA chips: Configurable dynamically-reconfigurable processors. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425711, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp. 384-387, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 07/11/12. https://doi.org/10.1109/ASSCC.2007.4425711

@inproceedings{5d1c2747231e47d08280cb4748e85622,

title = "MuCCRA chips: Configurable dynamically-reconfigurable processors",

abstract = "Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in System-On-Chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application. That is, DRPAs should be configurable for target SoCs and applications. MuCCRA is a project for developing a DRPA generator which can generate RTL model, testing environment and programming environment for various types of DRPAs just by selecting the specific parameters. Here, two prototype chips MuCCRA-1 and MuCCRA-2 developed in the project are introduced and evaluated. MuCCRA-1 was implemented with Rohm's 0.18um CMOS process mainly for multi-media applications, while MuCCRA-2 with ASPLA's 90nm CMOS process was designed focusing on area optimization used as a cost-effective IP in multi-core SoCs.",

author = "Hideharu Amano and Yohei Hasegawa and Satoshi Tsutsumi and Takuro Nakamura and Takashi Nishimura and Vasutan Tanbunheng and Aepu Parimala and Toru Sano and Masaru Kato",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/ASSCC.2007.4425711",

language = "English",

isbn = "1424413605",

series = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

pages = "384--387",

booktitle = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

note = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC ; Conference date: 12-11-2007 Through 14-11-2007",

}

TY - GEN

T1 - MuCCRA chips

T2 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

AU - Amano, Hideharu

AU - Hasegawa, Yohei

AU - Tsutsumi, Satoshi

AU - Nakamura, Takuro

AU - Nishimura, Takashi

AU - Tanbunheng, Vasutan

AU - Parimala, Aepu

AU - Sano, Toru

AU - Kato, Masaru

PY - 2007/12/1

Y1 - 2007/12/1

N2 - Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in System-On-Chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application. That is, DRPAs should be configurable for target SoCs and applications. MuCCRA is a project for developing a DRPA generator which can generate RTL model, testing environment and programming environment for various types of DRPAs just by selecting the specific parameters. Here, two prototype chips MuCCRA-1 and MuCCRA-2 developed in the project are introduced and evaluated. MuCCRA-1 was implemented with Rohm's 0.18um CMOS process mainly for multi-media applications, while MuCCRA-2 with ASPLA's 90nm CMOS process was designed focusing on area optimization used as a cost-effective IP in multi-core SoCs.

AB - Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in System-On-Chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application. That is, DRPAs should be configurable for target SoCs and applications. MuCCRA is a project for developing a DRPA generator which can generate RTL model, testing environment and programming environment for various types of DRPAs just by selecting the specific parameters. Here, two prototype chips MuCCRA-1 and MuCCRA-2 developed in the project are introduced and evaluated. MuCCRA-1 was implemented with Rohm's 0.18um CMOS process mainly for multi-media applications, while MuCCRA-2 with ASPLA's 90nm CMOS process was designed focusing on area optimization used as a cost-effective IP in multi-core SoCs.

UR - http://www.scopus.com/inward/record.url?scp=51349116937&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51349116937&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2007.4425711

DO - 10.1109/ASSCC.2007.4425711

M3 - Conference contribution

AN - SCOPUS:51349116937

SN - 1424413605

SN - 9781424413607

T3 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

SP - 384

EP - 387

BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Y2 - 12 November 2007 through 14 November 2007

ER -

MuCCRA chips: Configurable dynamically-reconfigurable processors

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