Body biasing can be used to control the leakage power and the performance of transistors by changing the threshold voltage after fabrication. Especially, a new process called Silicon-On-Thin BOX (SOTB) CMOS can control the balance of these two factors. When it is applied to a Coarse-Grained Reconfigurable Array (CGRA), the leakage power can be largely reduced by controlling precisely the bias with small domain size. On the other hand, the choices on bias voltages depend on the application executed on the platform, especially its mapping. In this paper, we propose to apply a multi-objective optimization for the application mapping and the body bias control on an energy efficient CGRA called CC-SOTB (Cool Mega Array Cube-SOTB). By using an NSGA-II algorithm for the mapping exploration and Integer Linear Programming (ILP) for the body bias control optimization, we show that it is possible to achieve better power consumption results than in previous works. For instance, in the case of a domain size of 2 rows by 1 column, it is possible to achieve a power reduction ratio up to 43.25%, compared to 21.09% previously, for the studied application. This is however achieved at the cost of a bigger mapping width. Nonetheless, the exploration allows to have finer analyses about both mapping and consumption. Indeed, these promising results show that optimizing the application mapping simultaneously with the body bias control can provide more interesting results, giving deeper quantitative information about trade-off possibilities.