Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

Yuta Tokusashi, Hiroki Matsutani

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Key-value store accelerators based on field-programmable gate arrays (FPGAs) have been proposed to achieve higher performance per watt than software-based processing. However, because their cache capacity is strictly limited by DRAMs implemented on FPGA boards, their application domains are also limited. To address this issue, the authors propose a multilevel NoSQL cache architecture that utilizes both FPGA-based hardware cache and in-kernel software cache in a complementary style. This motivates them to explore various design options. Simulation results show that their design reduces the cache miss ratio and improves the throughput compared to the nonhierarchical design.

Original languageEnglish
Article number8065000
Pages (from-to)44-51
Number of pages8
JournalIEEE Micro
Volume37
Issue number5
DOIs
Publication statusPublished - 2017 Sep 1

Fingerprint

Field programmable gate arrays (FPGA)
Dynamic random access storage
Particle accelerators
Throughput
Hardware
Processing

Keywords

  • field-programmable gate array
  • FPGA
  • key-value store
  • NoSQL

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches. / Tokusashi, Yuta; Matsutani, Hiroki.

In: IEEE Micro, Vol. 37, No. 5, 8065000, 01.09.2017, p. 44-51.

Research output: Contribution to journalArticle

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