Multistage interconnection networks with multiple outlets

Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

Multistage Interconnection Networks(MINs) with multiple outlets are networks which can support higher bandwidth than that of nonblocking networks by passing multiple packets to the same destination. A novel MIN topology with multiple outlets called Piled Banyan Switching Fabrics (PBSF) is proposed for the Simple Serial Synchronized (SSS)-MIN used in multiprocessors, and analyzed with other two types of MIN with multiple outlets called Multi-Banyan Switching Fabrics (MBSF) and Tandem Banyan Switching Fabrics (TBSF). The throughput of these MINs is evaluated and compared with both the theoretical model and simulation. The PBSF supports the best throughput and latency used for the SSS-MIN. Although the latency of the TBSF is large, the pass-through ratio is close to 1 if the number of connected banyan networks are more than 4. Therefore, the TBSF is useful for the ATM switching networks in which the relatively large latency is tolerable. The conflict-free access of these MINs is also analyzed, and it appears that rows, column, forward and backward diagonal of the matrix can be accessed without conflict.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume1
ISBN (Print)0849324939, 9780849324932
DOIs
Publication statusPublished - 1994
Event23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States
Duration: 1994 Aug 151994 Aug 19

Other

Other23rd International Conference on Parallel Processing, ICPP 1994
CountryUnited States
CityRaleigh, NC
Period94/8/1594/8/19

Fingerprint

Multistage Interconnection Networks
Latency
Throughput
Switching networks
Automatic teller machines
Multiprocessor
Network Topology
Theoretical Model
Topology
Bandwidth

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Cite this

Hanawa, T., Amano, H., & Fujikawa, Y. (1994). Multistage interconnection networks with multiple outlets. In Proceedings of the International Conference on Parallel Processing (Vol. 1). [4115682] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.1994.133

Multistage interconnection networks with multiple outlets. / Hanawa, Toshihiro; Amano, Hideharu; Fujikawa, Yoshifumi.

Proceedings of the International Conference on Parallel Processing. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1994. 4115682.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hanawa, T, Amano, H & Fujikawa, Y 1994, Multistage interconnection networks with multiple outlets. in Proceedings of the International Conference on Parallel Processing. vol. 1, 4115682, Institute of Electrical and Electronics Engineers Inc., 23rd International Conference on Parallel Processing, ICPP 1994, Raleigh, NC, United States, 94/8/15. https://doi.org/10.1109/ICPP.1994.133
Hanawa T, Amano H, Fujikawa Y. Multistage interconnection networks with multiple outlets. In Proceedings of the International Conference on Parallel Processing. Vol. 1. Institute of Electrical and Electronics Engineers Inc. 1994. 4115682 https://doi.org/10.1109/ICPP.1994.133
Hanawa, Toshihiro ; Amano, Hideharu ; Fujikawa, Yoshifumi. / Multistage interconnection networks with multiple outlets. Proceedings of the International Conference on Parallel Processing. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1994.
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