Namacha: A software development environment for a multi-chip convolutional network accelerator

Tetsui Ohkubo, Ryo Takata, Ryuichi Sakamoto, Masaaki Kondo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A building block convolutional neural network accelerator consists of a host and multiple accelerator chips which can scale the performance by changing the number of stacked chips. In order to program the host and the accelerators, an integrated programming development environment called NAMACHA is proposed. It includes compilers for convolutional neural network accelerators and a system level simulator including inter-chip communication latency. On the simulator, the total application runs 4390x faster than that of the logic level simulation with 1.27% difference of clock cycle counts.

Original languageEnglish
Title of host publicationProceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017
PublisherThe International Society for Computers and Their Applications (ISCA)
Pages101-106
Number of pages6
ISBN (Electronic)9781943436064
Publication statusPublished - 2017
Event32nd International Conference on Computers and Their Applications, CATA 2017 - Honolulu, United States
Duration: 2017 Mar 202017 Mar 22

Other

Other32nd International Conference on Computers and Their Applications, CATA 2017
CountryUnited States
CityHonolulu
Period17/3/2017/3/22

ASJC Scopus subject areas

  • Computer Science Applications

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  • Cite this

    Ohkubo, T., Takata, R., Sakamoto, R., Kondo, M., & Amano, H. (2017). Namacha: A software development environment for a multi-chip convolutional network accelerator. In Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017 (pp. 101-106). The International Society for Computers and Their Applications (ISCA).