Near-optimal parallel algorithm for one-dimensional gate assignment in VLSI layout

K. Tsuchiya; Y. Takefuji

doi:10.3233/ica-1999-6306

Near-optimal parallel algorithm for one-dimensional gate assignment in VLSI layout

K. Tsuchiya, Y. Takefuji

Faculty of Environment and Information Studies

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

A novel approach to the one-dimensional gate assignment problem is presented in this paper where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n×n processing elements called the artificial two-dimensional maximum neurons for (n+2)-gate assignment problems. We have discovered the improved solutions in the benchmark problems over the best existing algorithms. The proposed parallel algorithm is also applicable to other VLSI layout problems.

Original language	English
Pages (from-to)	249-257
Number of pages	9
Journal	Integrated Computer-Aided Engineering
Volume	6
Issue number	3
DOIs	https://doi.org/10.3233/ica-1999-6306
Publication status	Published - 1999

ASJC Scopus subject areas

Software
Theoretical Computer Science
Computer Science Applications
Computational Theory and Mathematics
Artificial Intelligence

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