Near-optimal parallel algorithm for one-dimensional gate assignment in VLSI layout

K. Tsuchiya, Yoshiyasu Takefuji

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A novel approach to the one-dimensional gate assignment problem is presented in this paper where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n×n processing elements called the artificial two-dimensional maximum neurons for (n+2)-gate assignment problems. We have discovered the improved solutions in the benchmark problems over the best existing algorithms. The proposed parallel algorithm is also applicable to other VLSI layout problems.

Original languageEnglish
Pages (from-to)249-257
Number of pages9
JournalIntegrated Computer-Aided Engineering
Volume6
Issue number3
Publication statusPublished - 1999

Fingerprint

VLSI Layout
Optimal Algorithm
Parallel algorithms
Parallel Algorithms
Neurons
Computational complexity
Assignment
Assignment Problem
Processing
VLSI Design
Layout
Neuron
NP-complete problem
Benchmark

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computational Theory and Mathematics
  • Computer Science Applications
  • Engineering (miscellaneous)

Cite this

Near-optimal parallel algorithm for one-dimensional gate assignment in VLSI layout. / Tsuchiya, K.; Takefuji, Yoshiyasu.

In: Integrated Computer-Aided Engineering, Vol. 6, No. 3, 1999, p. 249-257.

Research output: Contribution to journalArticle

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