Abstract
A novel approach to the one-dimensional gate assignment problem is presented in this paper where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n×n processing elements called the artificial two-dimensional maximum neurons for (n+2)-gate assignment problems. We have discovered the improved solutions in the benchmark problems over the best existing algorithms. The proposed parallel algorithm is also applicable to other VLSI layout problems.
| Original language | English |
|---|---|
| Pages (from-to) | 249-257 |
| Number of pages | 9 |
| Journal | Integrated Computer-Aided Engineering |
| Volume | 6 |
| Issue number | 3 |
| Publication status | Published - 1999 |
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ASJC Scopus subject areas
- Artificial Intelligence
- Computational Theory and Mathematics
- Computer Science Applications
- Engineering (miscellaneous)
Cite this
Near-optimal parallel algorithm for one-dimensional gate assignment in VLSI layout. / Tsuchiya, K.; Takefuji, Yoshiyasu.
In: Integrated Computer-Aided Engineering, Vol. 6, No. 3, 1999, p. 249-257.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Near-optimal parallel algorithm for one-dimensional gate assignment in VLSI layout
AU - Tsuchiya, K.
AU - Takefuji, Yoshiyasu
PY - 1999
Y1 - 1999
N2 - A novel approach to the one-dimensional gate assignment problem is presented in this paper where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n×n processing elements called the artificial two-dimensional maximum neurons for (n+2)-gate assignment problems. We have discovered the improved solutions in the benchmark problems over the best existing algorithms. The proposed parallel algorithm is also applicable to other VLSI layout problems.
AB - A novel approach to the one-dimensional gate assignment problem is presented in this paper where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n×n processing elements called the artificial two-dimensional maximum neurons for (n+2)-gate assignment problems. We have discovered the improved solutions in the benchmark problems over the best existing algorithms. The proposed parallel algorithm is also applicable to other VLSI layout problems.
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UR - http://www.scopus.com/inward/citedby.url?scp=0032598765&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0032598765
VL - 6
SP - 249
EP - 257
JO - Integrated Computer-Aided Engineering
JF - Integrated Computer-Aided Engineering
SN - 1069-2509
IS - 3
ER -