TY - JOUR
T1 - Neural network parallel algorithm for one-dimensional gate assignment problems
AU - Tsuchiya, Kazuhiro
AU - Takefuji, Yoshiyasu
AU - Kurotani, Ken Ichi
PY - 1999/11/15
Y1 - 1999/11/15
N2 - A near-optimum parallel algorithm for solving the one-dimensional gate assignment problem is presented in this paper, where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n×n processing elements based on the artificial two-dimensional maximum neural network for (n+2)-gate assignment problems. Our algorithm has discovered improved solutions in the benchmark problems compared with the best existing algorithms. The proposed approach is applicable to other VLSI layout problems such as the PLA (Programmable Logic Array) folding problem.
AB - A near-optimum parallel algorithm for solving the one-dimensional gate assignment problem is presented in this paper, where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n×n processing elements based on the artificial two-dimensional maximum neural network for (n+2)-gate assignment problems. Our algorithm has discovered improved solutions in the benchmark problems compared with the best existing algorithms. The proposed approach is applicable to other VLSI layout problems such as the PLA (Programmable Logic Array) folding problem.
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U2 - 10.1002/(SICI)1520-6416(19991115)129:2<71::AID-EEJ8>3.0.CO;2-D
DO - 10.1002/(SICI)1520-6416(19991115)129:2<71::AID-EEJ8>3.0.CO;2-D
M3 - Article
AN - SCOPUS:0032657545
SN - 0424-7760
VL - 129
SP - 71
EP - 77
JO - Electrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)
JF - Electrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)
IS - 2
ER -