Neural network parallel algorithm for one-dimensional gate assignment problems

Kazuhiro Tsuchiya, Yoshiyasu Takefuji, Ken Ichi Kurotani

Research output: Contribution to journalArticlepeer-review


A near-optimum parallel algorithm for solving the one-dimensional gate assignment problem is presented in this paper, where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n×n processing elements based on the artificial two-dimensional maximum neural network for (n+2)-gate assignment problems. Our algorithm has discovered improved solutions in the benchmark problems compared with the best existing algorithms. The proposed approach is applicable to other VLSI layout problems such as the PLA (Programmable Logic Array) folding problem.

Original languageEnglish
Pages (from-to)71-77
Number of pages7
JournalElectrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)
Issue number2
Publication statusPublished - 1999 Nov 15
Externally publishedYes

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering


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