### Abstract

Neural network parallel computing for balanced incomplete block design (BIBD) problems is presented. A design in which all the blocks contain the same number of varieties, and all the varieties occur in the same number of blocks, is called a block design. A block is said to be incomplete if it does not contain all the varieties. If a design is balanced, it is called a balanced incomplete block design. Two methods for BIBD problems have been proposed. One uses the notion of the finite fields, and the other uses the notion of the difference sets. In general, the conventional algorithms are only able to solve the problems that satisfy an affine plane or a finite projective plane. The proposed algorithm is able to solve BIBD problems regardless of the condition of an affine plane or a finite projective plane. The proposed algorithm was verified by simulation runs. The simulation results demonstrated that the number of iteration steps for the system to converge to the solution increases slightly with the problem size.

Original language | English |
---|---|

Pages (from-to) | 243-247 |

Number of pages | 5 |

Journal | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |

Volume | 39 |

Issue number | 4 |

DOIs | |

Publication status | Published - 1992 Apr |

Externally published | Yes |

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### ASJC Scopus subject areas

- Signal Processing
- Electrical and Electronic Engineering

### Cite this

**Neural network parallel computing for BIBD problems.** / Kurokawa, Takakazu; Takefuji, Yoshiyasu.

Research output: Contribution to journal › Article

*IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing*, vol. 39, no. 4, pp. 243-247. https://doi.org/10.1109/82.136575

}

TY - JOUR

T1 - Neural network parallel computing for BIBD problems

AU - Kurokawa, Takakazu

AU - Takefuji, Yoshiyasu

PY - 1992/4

Y1 - 1992/4

N2 - Neural network parallel computing for balanced incomplete block design (BIBD) problems is presented. A design in which all the blocks contain the same number of varieties, and all the varieties occur in the same number of blocks, is called a block design. A block is said to be incomplete if it does not contain all the varieties. If a design is balanced, it is called a balanced incomplete block design. Two methods for BIBD problems have been proposed. One uses the notion of the finite fields, and the other uses the notion of the difference sets. In general, the conventional algorithms are only able to solve the problems that satisfy an affine plane or a finite projective plane. The proposed algorithm is able to solve BIBD problems regardless of the condition of an affine plane or a finite projective plane. The proposed algorithm was verified by simulation runs. The simulation results demonstrated that the number of iteration steps for the system to converge to the solution increases slightly with the problem size.

AB - Neural network parallel computing for balanced incomplete block design (BIBD) problems is presented. A design in which all the blocks contain the same number of varieties, and all the varieties occur in the same number of blocks, is called a block design. A block is said to be incomplete if it does not contain all the varieties. If a design is balanced, it is called a balanced incomplete block design. Two methods for BIBD problems have been proposed. One uses the notion of the finite fields, and the other uses the notion of the difference sets. In general, the conventional algorithms are only able to solve the problems that satisfy an affine plane or a finite projective plane. The proposed algorithm is able to solve BIBD problems regardless of the condition of an affine plane or a finite projective plane. The proposed algorithm was verified by simulation runs. The simulation results demonstrated that the number of iteration steps for the system to converge to the solution increases slightly with the problem size.

UR - http://www.scopus.com/inward/record.url?scp=0026850749&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026850749&partnerID=8YFLogxK

U2 - 10.1109/82.136575

DO - 10.1109/82.136575

M3 - Article

VL - 39

SP - 243

EP - 247

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1057-7130

IS - 4

ER -