Non-volatile doubly stacked Si dot memory

R. Ohba, N. Sugiyama, Ken Uchida, J. Koga, S. Fujita, A. Toriumi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In the Si dot memory, the realization of a long retention time is the most critical issue, since the tunnel oxide is very thin. So as to realize a long retention time without losing high-speed w/e in Si dot memory, we propose a novel Si dot memory whose floating gates are doubly stacked Si dots. A long retention time is possible, since the charge leak between the upper dots and the channel is suppressed due to quantum confinement and Coulomb blockade in the lower dot. Simultaneously, a high-speed w/e is possible, since the leak suppression is useful only in a low voltage region. Therefore, Si double dot memory is very promising for low-power non-volatile memory.

Original languageEnglish
Title of host publication2002 International Microprocesses and Nanotechnology Conference, MNC 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages56-57
Number of pages2
ISBN (Print)4891140313, 9784891140311
DOIs
Publication statusPublished - 2002
Externally publishedYes
EventInternational Microprocesses and Nanotechnology Conference, MNC 2002 - Tokyo, Japan
Duration: 2002 Nov 62002 Nov 8

Other

OtherInternational Microprocesses and Nanotechnology Conference, MNC 2002
CountryJapan
CityTokyo
Period02/11/602/11/8

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ohba, R., Sugiyama, N., Uchida, K., Koga, J., Fujita, S., & Toriumi, A. (2002). Non-volatile doubly stacked Si dot memory. In 2002 International Microprocesses and Nanotechnology Conference, MNC 2002 (pp. 56-57). [1178541] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IMNC.2002.1178541