Abstract
In the Si dot memory, the realization of a long retention time is the most critical issue, since the tunnel oxide is very thin. So as to realize a long retention time without losing high-speed w/e in Si dot memory, we propose a novel Si dot memory whose floating gates are doubly stacked Si dots. A long retention time is possible, since the charge leak between the upper dots and the channel is suppressed due to quantum confinement and Coulomb blockade in the lower dot. Simultaneously, a high-speed w/e is possible, since the leak suppression is useful only in a low voltage region. Therefore, Si double dot memory is very promising for low-power non-volatile memory.
| Original language | English |
|---|---|
| Title of host publication | 2002 International Microprocesses and Nanotechnology Conference, MNC 2002 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 56-57 |
| Number of pages | 2 |
| ISBN (Print) | 4891140313, 9784891140311 |
| DOIs | |
| Publication status | Published - 2002 |
| Externally published | Yes |
| Event | International Microprocesses and Nanotechnology Conference, MNC 2002 - Tokyo, Japan Duration: 2002 Nov 6 → 2002 Nov 8 |
Other
| Other | International Microprocesses and Nanotechnology Conference, MNC 2002 |
|---|---|
| Country | Japan |
| City | Tokyo |
| Period | 02/11/6 → 02/11/8 |
Fingerprint
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Non-volatile doubly stacked Si dot memory. / Ohba, R.; Sugiyama, N.; Uchida, Ken; Koga, J.; Fujita, S.; Toriumi, A.
2002 International Microprocesses and Nanotechnology Conference, MNC 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 56-57 1178541.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Non-volatile doubly stacked Si dot memory
AU - Ohba, R.
AU - Sugiyama, N.
AU - Uchida, Ken
AU - Koga, J.
AU - Fujita, S.
AU - Toriumi, A.
PY - 2002
Y1 - 2002
N2 - In the Si dot memory, the realization of a long retention time is the most critical issue, since the tunnel oxide is very thin. So as to realize a long retention time without losing high-speed w/e in Si dot memory, we propose a novel Si dot memory whose floating gates are doubly stacked Si dots. A long retention time is possible, since the charge leak between the upper dots and the channel is suppressed due to quantum confinement and Coulomb blockade in the lower dot. Simultaneously, a high-speed w/e is possible, since the leak suppression is useful only in a low voltage region. Therefore, Si double dot memory is very promising for low-power non-volatile memory.
AB - In the Si dot memory, the realization of a long retention time is the most critical issue, since the tunnel oxide is very thin. So as to realize a long retention time without losing high-speed w/e in Si dot memory, we propose a novel Si dot memory whose floating gates are doubly stacked Si dots. A long retention time is possible, since the charge leak between the upper dots and the channel is suppressed due to quantum confinement and Coulomb blockade in the lower dot. Simultaneously, a high-speed w/e is possible, since the leak suppression is useful only in a low voltage region. Therefore, Si double dot memory is very promising for low-power non-volatile memory.
UR - http://www.scopus.com/inward/record.url?scp=84960465849&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84960465849&partnerID=8YFLogxK
U2 - 10.1109/IMNC.2002.1178541
DO - 10.1109/IMNC.2002.1178541
M3 - Conference contribution
AN - SCOPUS:84960465849
SN - 4891140313
SN - 9784891140311
SP - 56
EP - 57
BT - 2002 International Microprocesses and Nanotechnology Conference, MNC 2002
PB - Institute of Electrical and Electronics Engineers Inc.
ER -