Non-volatile doubly stacked Si dot memory

R. Ohba; N. Sugiyama; Ken Uchida; J. Koga; S. Fujita; A. Toriumi

doi:10.1109/IMNC.2002.1178541

Non-volatile doubly stacked Si dot memory

R. Ohba, N. Sugiyama, Ken Uchida, J. Koga, S. Fujita, A. Toriumi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In the Si dot memory, the realization of a long retention time is the most critical issue, since the tunnel oxide is very thin. So as to realize a long retention time without losing high-speed w/e in Si dot memory, we propose a novel Si dot memory whose floating gates are doubly stacked Si dots. A long retention time is possible, since the charge leak between the upper dots and the channel is suppressed due to quantum confinement and Coulomb blockade in the lower dot. Simultaneously, a high-speed w/e is possible, since the leak suppression is useful only in a low voltage region. Therefore, Si double dot memory is very promising for low-power non-volatile memory.

Original language	English
Title of host publication	2002 International Microprocesses and Nanotechnology Conference, MNC 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	56-57
Number of pages	2
ISBN (Print)	4891140313, 9784891140311
DOIs	https://doi.org/10.1109/IMNC.2002.1178541
Publication status	Published - 2002
Externally published	Yes
Event	International Microprocesses and Nanotechnology Conference, MNC 2002 - Tokyo, Japan Duration: 2002 Nov 6 → 2002 Nov 8

Other

Other	International Microprocesses and Nanotechnology Conference, MNC 2002
Country/Territory	Japan
City	Tokyo
Period	02/11/6 → 02/11/8

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/IMNC.2002.1178541

Cite this

Ohba, R, Sugiyama, N, Uchida, K, Koga, J, Fujita, S & Toriumi, A 2002, Non-volatile doubly stacked Si dot memory. in 2002 International Microprocesses and Nanotechnology Conference, MNC 2002., 1178541, Institute of Electrical and Electronics Engineers Inc., pp. 56-57, International Microprocesses and Nanotechnology Conference, MNC 2002, Tokyo, Japan, 02/11/6. https://doi.org/10.1109/IMNC.2002.1178541

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title = "Non-volatile doubly stacked Si dot memory",

abstract = "In the Si dot memory, the realization of a long retention time is the most critical issue, since the tunnel oxide is very thin. So as to realize a long retention time without losing high-speed w/e in Si dot memory, we propose a novel Si dot memory whose floating gates are doubly stacked Si dots. A long retention time is possible, since the charge leak between the upper dots and the channel is suppressed due to quantum confinement and Coulomb blockade in the lower dot. Simultaneously, a high-speed w/e is possible, since the leak suppression is useful only in a low voltage region. Therefore, Si double dot memory is very promising for low-power non-volatile memory.",

author = "R. Ohba and N. Sugiyama and Ken Uchida and J. Koga and S. Fujita and A. Toriumi",

year = "2002",

doi = "10.1109/IMNC.2002.1178541",

language = "English",

isbn = "4891140313",

pages = "56--57",

booktitle = "2002 International Microprocesses and Nanotechnology Conference, MNC 2002",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "International Microprocesses and Nanotechnology Conference, MNC 2002 ; Conference date: 06-11-2002 Through 08-11-2002",

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T1 - Non-volatile doubly stacked Si dot memory

AU - Ohba, R.

AU - Sugiyama, N.

AU - Uchida, Ken

AU - Koga, J.

AU - Fujita, S.

AU - Toriumi, A.

PY - 2002

Y1 - 2002

N2 - In the Si dot memory, the realization of a long retention time is the most critical issue, since the tunnel oxide is very thin. So as to realize a long retention time without losing high-speed w/e in Si dot memory, we propose a novel Si dot memory whose floating gates are doubly stacked Si dots. A long retention time is possible, since the charge leak between the upper dots and the channel is suppressed due to quantum confinement and Coulomb blockade in the lower dot. Simultaneously, a high-speed w/e is possible, since the leak suppression is useful only in a low voltage region. Therefore, Si double dot memory is very promising for low-power non-volatile memory.

AB - In the Si dot memory, the realization of a long retention time is the most critical issue, since the tunnel oxide is very thin. So as to realize a long retention time without losing high-speed w/e in Si dot memory, we propose a novel Si dot memory whose floating gates are doubly stacked Si dots. A long retention time is possible, since the charge leak between the upper dots and the channel is suppressed due to quantum confinement and Coulomb blockade in the lower dot. Simultaneously, a high-speed w/e is possible, since the leak suppression is useful only in a low voltage region. Therefore, Si double dot memory is very promising for low-power non-volatile memory.

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SN - 9784891140311

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EP - 57

BT - 2002 International Microprocesses and Nanotechnology Conference, MNC 2002

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - International Microprocesses and Nanotechnology Conference, MNC 2002

Y2 - 6 November 2002 through 8 November 2002

ER -

Non-volatile doubly stacked Si dot memory

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