On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Technology scaling makes designers face difficulties dealing with wire delay of long global interconnects, especially for high-radix networks. In this context, we propose decentralization of on-chip packet routers. A decentralized router consists of submodules, each of which has particular functionality and they are scattered on a link, thereby long wires are segmented. Our starting point is from a conventional router architecture, and we illustrate four case studies to generalize our proposal. We also propose a new buffer design and how to balance pipelines of a router. A proof-of-concept is shown in 28-nm process technology. Our results demonstrate that the decentralization of an on-chip router enables Link Traversal (LT) stages to be eliminated, and the critical path delay is improved by up to 45% with the reduced area compared with a conventional router. As technology advances, the benefit of the decentralized routers become more substantial in the nano-scale era.

Original languageEnglish
Title of host publicationProceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450333962
DOIs
Publication statusPublished - 2015 Sep 28
Event9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015 - Vancouver, Canada
Duration: 2015 Sep 282015 Sep 30

Other

Other9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
CountryCanada
CityVancouver
Period15/9/2815/9/30

Fingerprint

Routers
Pipelines
Wire

Keywords

  • Decentralized router
  • Delay model
  • Interconnect bottleneck
  • Interconnection networks
  • Router architecture
  • Wire delay

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yasudo, R., Matsutani, H., Koibuchi, M., Amano, H., & Nakamura, T. (2015). On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck. In Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015 [2817280] Association for Computing Machinery, Inc. https://doi.org/10.1145/2786572.2786583

On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck. / Yasudo, Ryota; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu; Nakamura, Tadao.

Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015. Association for Computing Machinery, Inc, 2015. 2817280.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yasudo, R, Matsutani, H, Koibuchi, M, Amano, H & Nakamura, T 2015, On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck. in Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015., 2817280, Association for Computing Machinery, Inc, 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, Canada, 15/9/28. https://doi.org/10.1145/2786572.2786583
Yasudo R, Matsutani H, Koibuchi M, Amano H, Nakamura T. On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck. In Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015. Association for Computing Machinery, Inc. 2015. 2817280 https://doi.org/10.1145/2786572.2786583
Yasudo, Ryota ; Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu ; Nakamura, Tadao. / On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck. Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015. Association for Computing Machinery, Inc, 2015.
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