Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We introduce a novel graph called a host-switch graph, which consists of host vertices and switch vertices. Using host-switch graphs, we formulate a graph problem called an order/radix problem (ORP) for designing low end-to-end latency interconnection networks. Our focus is on reducing the host-to-host average shortest path length (h-ASPL), since the shortest path length between hosts in a host-switch graph corresponds to the end-to-end latency of a network. We hence define ORP as follows: given order (the number of hosts) and radix (the number of ports per switch), find a host-switch graph with the minimum h-ASPL. We demonstrate that the optimal number of switches can mathematically be predicted. On the basis of the prediction, we carry out a randomized algorithm to find a host-switch graph with the minimum h-ASPL. Interestingly, our solutions include a host-switch graph such that switches have the different number of hosts. We then apply host-switch graphs to interconnection networks and evaluate them practically. As compared with the three conventional interconnection networks (the torus, the dragonfly, and the fat-tree), we demonstrate that our networks provide higher performance while the number of switches can decrease.

Original languageEnglish
Title of host publicationProceedings - 46th International Conference on Parallel Processing, ICPP 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages322-331
Number of pages10
ISBN (Electronic)9781538610428
DOIs
Publication statusPublished - 2017 Sep 1
Event46th International Conference on Parallel Processing, ICPP 2017 - Bristol, United Kingdom
Duration: 2017 Aug 142017 Aug 17

Other

Other46th International Conference on Parallel Processing, ICPP 2017
CountryUnited Kingdom
CityBristol
Period17/8/1417/8/17

Fingerprint

Interconnection Networks
Latency
Switch
Switches
Graph in graph theory
Path Length
Shortest path
Network Performance
Randomized Algorithms
Oils and fats
Demonstrate
Torus
High Performance

Keywords

  • Average shortest path length
  • Graph theory
  • Interconnection network
  • Network topology
  • Optimization

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Cite this

Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H., & Amano, H. (2017). Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. In Proceedings - 46th International Conference on Parallel Processing, ICPP 2017 (pp. 322-331). [8025306] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.2017.41

Order/Radix Problem : Towards Low End-to-End Latency Interconnection Networks. / Yasudo, Ryota; Koibuchi, Michihiro; Nakano, Koji; Matsutani, Hiroki; Amano, Hideharu.

Proceedings - 46th International Conference on Parallel Processing, ICPP 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 322-331 8025306.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yasudo, R, Koibuchi, M, Nakano, K, Matsutani, H & Amano, H 2017, Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. in Proceedings - 46th International Conference on Parallel Processing, ICPP 2017., 8025306, Institute of Electrical and Electronics Engineers Inc., pp. 322-331, 46th International Conference on Parallel Processing, ICPP 2017, Bristol, United Kingdom, 17/8/14. https://doi.org/10.1109/ICPP.2017.41
Yasudo R, Koibuchi M, Nakano K, Matsutani H, Amano H. Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. In Proceedings - 46th International Conference on Parallel Processing, ICPP 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 322-331. 8025306 https://doi.org/10.1109/ICPP.2017.41
Yasudo, Ryota ; Koibuchi, Michihiro ; Nakano, Koji ; Matsutani, Hiroki ; Amano, Hideharu. / Order/Radix Problem : Towards Low End-to-End Latency Interconnection Networks. Proceedings - 46th International Conference on Parallel Processing, ICPP 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 322-331
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