### Abstract

We introduce a novel graph called a host-switch graph, which consists of host vertices and switch vertices. Using host-switch graphs, we formulate a graph problem called an order/radix problem (ORP) for designing low end-to-end latency interconnection networks. Our focus is on reducing the host-to-host average shortest path length (h-ASPL), since the shortest path length between hosts in a host-switch graph corresponds to the end-to-end latency of a network. We hence define ORP as follows: given order (the number of hosts) and radix (the number of ports per switch), find a host-switch graph with the minimum h-ASPL. We demonstrate that the optimal number of switches can mathematically be predicted. On the basis of the prediction, we carry out a randomized algorithm to find a host-switch graph with the minimum h-ASPL. Interestingly, our solutions include a host-switch graph such that switches have the different number of hosts. We then apply host-switch graphs to interconnection networks and evaluate them practically. As compared with the three conventional interconnection networks (the torus, the dragonfly, and the fat-tree), we demonstrate that our networks provide higher performance while the number of switches can decrease.

Original language | English |
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Title of host publication | Proceedings - 46th International Conference on Parallel Processing, ICPP 2017 |

Publisher | Institute of Electrical and Electronics Engineers Inc. |

Pages | 322-331 |

Number of pages | 10 |

ISBN (Electronic) | 9781538610428 |

DOIs | |

Publication status | Published - 2017 Sep 1 |

Event | 46th International Conference on Parallel Processing, ICPP 2017 - Bristol, United Kingdom Duration: 2017 Aug 14 → 2017 Aug 17 |

### Other

Other | 46th International Conference on Parallel Processing, ICPP 2017 |
---|---|

Country | United Kingdom |

City | Bristol |

Period | 17/8/14 → 17/8/17 |

### Fingerprint

### Keywords

- Average shortest path length
- Graph theory
- Interconnection network
- Network topology
- Optimization

### ASJC Scopus subject areas

- Software
- Mathematics(all)
- Hardware and Architecture

### Cite this

*Proceedings - 46th International Conference on Parallel Processing, ICPP 2017*(pp. 322-331). [8025306] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.2017.41

**Order/Radix Problem : Towards Low End-to-End Latency Interconnection Networks.** / Yasudo, Ryota; Koibuchi, Michihiro; Nakano, Koji; Matsutani, Hiroki; Amano, Hideharu.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings - 46th International Conference on Parallel Processing, ICPP 2017.*, 8025306, Institute of Electrical and Electronics Engineers Inc., pp. 322-331, 46th International Conference on Parallel Processing, ICPP 2017, Bristol, United Kingdom, 17/8/14. https://doi.org/10.1109/ICPP.2017.41

}

TY - GEN

T1 - Order/Radix Problem

T2 - Towards Low End-to-End Latency Interconnection Networks

AU - Yasudo, Ryota

AU - Koibuchi, Michihiro

AU - Nakano, Koji

AU - Matsutani, Hiroki

AU - Amano, Hideharu

PY - 2017/9/1

Y1 - 2017/9/1

N2 - We introduce a novel graph called a host-switch graph, which consists of host vertices and switch vertices. Using host-switch graphs, we formulate a graph problem called an order/radix problem (ORP) for designing low end-to-end latency interconnection networks. Our focus is on reducing the host-to-host average shortest path length (h-ASPL), since the shortest path length between hosts in a host-switch graph corresponds to the end-to-end latency of a network. We hence define ORP as follows: given order (the number of hosts) and radix (the number of ports per switch), find a host-switch graph with the minimum h-ASPL. We demonstrate that the optimal number of switches can mathematically be predicted. On the basis of the prediction, we carry out a randomized algorithm to find a host-switch graph with the minimum h-ASPL. Interestingly, our solutions include a host-switch graph such that switches have the different number of hosts. We then apply host-switch graphs to interconnection networks and evaluate them practically. As compared with the three conventional interconnection networks (the torus, the dragonfly, and the fat-tree), we demonstrate that our networks provide higher performance while the number of switches can decrease.

AB - We introduce a novel graph called a host-switch graph, which consists of host vertices and switch vertices. Using host-switch graphs, we formulate a graph problem called an order/radix problem (ORP) for designing low end-to-end latency interconnection networks. Our focus is on reducing the host-to-host average shortest path length (h-ASPL), since the shortest path length between hosts in a host-switch graph corresponds to the end-to-end latency of a network. We hence define ORP as follows: given order (the number of hosts) and radix (the number of ports per switch), find a host-switch graph with the minimum h-ASPL. We demonstrate that the optimal number of switches can mathematically be predicted. On the basis of the prediction, we carry out a randomized algorithm to find a host-switch graph with the minimum h-ASPL. Interestingly, our solutions include a host-switch graph such that switches have the different number of hosts. We then apply host-switch graphs to interconnection networks and evaluate them practically. As compared with the three conventional interconnection networks (the torus, the dragonfly, and the fat-tree), we demonstrate that our networks provide higher performance while the number of switches can decrease.

KW - Average shortest path length

KW - Graph theory

KW - Interconnection network

KW - Network topology

KW - Optimization

UR - http://www.scopus.com/inward/record.url?scp=85030642879&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85030642879&partnerID=8YFLogxK

U2 - 10.1109/ICPP.2017.41

DO - 10.1109/ICPP.2017.41

M3 - Conference contribution

AN - SCOPUS:85030642879

SP - 322

EP - 331

BT - Proceedings - 46th International Conference on Parallel Processing, ICPP 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -