Overview of low-power ULSI circuit techniques

Tadahiro Kuroda, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSls now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static circuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

Original languageEnglish
Title of host publicationHigh-Performance System Design
Subtitle of host publicationCircuits and Logic
PublisherJohn Wiley and Sons Inc.
Pages198-207
Number of pages10
ISBN (Electronic)9780470544846
ISBN (Print)0780347161, 9780780347168
DOIs
Publication statusPublished - 1999 Jan 1
Externally publishedYes

Fingerprint

ULSI circuits
Energy dissipation
Electric potential
Capacitance
Networks (circuits)
Transistors
LSI circuits
Electric network topology

Keywords

  • CMOS
  • Energy-delay product
  • Low-power
  • Low-voltage
  • LSI
  • Pass-transistor logic
  • Power-delay product

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

Cite this

Kuroda, T., & Sakurai, T. (1999). Overview of low-power ULSI circuit techniques. In High-Performance System Design: Circuits and Logic (pp. 198-207). John Wiley and Sons Inc.. https://doi.org/10.1109/9780470544846.ch3

Overview of low-power ULSI circuit techniques. / Kuroda, Tadahiro; Sakurai, Takayasu.

High-Performance System Design: Circuits and Logic. John Wiley and Sons Inc., 1999. p. 198-207.

Research output: Chapter in Book/Report/Conference proceedingChapter

Kuroda, T & Sakurai, T 1999, Overview of low-power ULSI circuit techniques. in High-Performance System Design: Circuits and Logic. John Wiley and Sons Inc., pp. 198-207. https://doi.org/10.1109/9780470544846.ch3
Kuroda T, Sakurai T. Overview of low-power ULSI circuit techniques. In High-Performance System Design: Circuits and Logic. John Wiley and Sons Inc. 1999. p. 198-207 https://doi.org/10.1109/9780470544846.ch3
Kuroda, Tadahiro ; Sakurai, Takayasu. / Overview of low-power ULSI circuit techniques. High-Performance System Design: Circuits and Logic. John Wiley and Sons Inc., 1999. pp. 198-207
@inbook{40829ea8e39049698ef2ebb00405744d,
title = "Overview of low-power ULSI circuit techniques",
abstract = "This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSls now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static circuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.",
keywords = "CMOS, Energy-delay product, Low-power, Low-voltage, LSI, Pass-transistor logic, Power-delay product",
author = "Tadahiro Kuroda and Takayasu Sakurai",
year = "1999",
month = "1",
day = "1",
doi = "10.1109/9780470544846.ch3",
language = "English",
isbn = "0780347161",
pages = "198--207",
booktitle = "High-Performance System Design",
publisher = "John Wiley and Sons Inc.",
address = "United States",

}

TY - CHAP

T1 - Overview of low-power ULSI circuit techniques

AU - Kuroda, Tadahiro

AU - Sakurai, Takayasu

PY - 1999/1/1

Y1 - 1999/1/1

N2 - This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSls now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static circuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

AB - This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSls now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static circuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

KW - CMOS

KW - Energy-delay product

KW - Low-power

KW - Low-voltage

KW - LSI

KW - Pass-transistor logic

KW - Power-delay product

UR - http://www.scopus.com/inward/record.url?scp=85037071377&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85037071377&partnerID=8YFLogxK

U2 - 10.1109/9780470544846.ch3

DO - 10.1109/9780470544846.ch3

M3 - Chapter

SN - 0780347161

SN - 9780780347168

SP - 198

EP - 207

BT - High-Performance System Design

PB - John Wiley and Sons Inc.

ER -