P-WELL/N-WELL COMPATIBLE CMOS PROCESSING FOR ASIC APPLICATIONS.

Tadahiro Kuroda, Hiroyuki Akiba, Hiroaki Suzuki, Takao Aoki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes p-well/n-well compatible CMOS device structure and processing for ASIC applications, together with a design methodology and a scaling scenario. Process optimization has been carried out with careful adjustment of impurity profiles. Equivalent characteristics have been realized in both processes in regard to transistor characteristics, speed performance and latch-up immunity. Scaling philosophy has also been established and its properties are demonstrated.

Original languageEnglish
Title of host publicationConference on Solid State Devices and Materials
PublisherBusiness Cent for Academic Soc Japan
Pages57-60
Number of pages4
ISBN (Print)493081314X
Publication statusPublished - 1986 Dec 1
Externally publishedYes

Publication series

NameConference on Solid State Devices and Materials

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Kuroda, T., Akiba, H., Suzuki, H., & Aoki, T. (1986). P-WELL/N-WELL COMPATIBLE CMOS PROCESSING FOR ASIC APPLICATIONS. In Conference on Solid State Devices and Materials (pp. 57-60). (Conference on Solid State Devices and Materials). Business Cent for Academic Soc Japan.