P-WELL/N-WELL COMPATIBLE CMOS PROCESSING FOR ASIC APPLICATIONS.

Tadahiro Kuroda; Hiroyuki Akiba; Hiroaki Suzuki; Takao Aoki

P-WELL/N-WELL COMPATIBLE CMOS PROCESSING FOR ASIC APPLICATIONS.

Tadahiro Kuroda, Hiroyuki Akiba, Hiroaki Suzuki, Takao Aoki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes p-well/n-well compatible CMOS device structure and processing for ASIC applications, together with a design methodology and a scaling scenario. Process optimization has been carried out with careful adjustment of impurity profiles. Equivalent characteristics have been realized in both processes in regard to transistor characteristics, speed performance and latch-up immunity. Scaling philosophy has also been established and its properties are demonstrated.

Original language	English
Title of host publication	Conference on Solid State Devices and Materials
Publisher	Business Cent for Academic Soc Japan
Pages	57-60
Number of pages	4
ISBN (Print)	493081314X
Publication status	Published - 1986 Dec 1
Externally published	Yes

Publication series

Name	Conference on Solid State Devices and Materials

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "P-WELL/N-WELL COMPATIBLE CMOS PROCESSING FOR ASIC APPLICATIONS.",

abstract = "This paper describes p-well/n-well compatible CMOS device structure and processing for ASIC applications, together with a design methodology and a scaling scenario. Process optimization has been carried out with careful adjustment of impurity profiles. Equivalent characteristics have been realized in both processes in regard to transistor characteristics, speed performance and latch-up immunity. Scaling philosophy has also been established and its properties are demonstrated.",

author = "Tadahiro Kuroda and Hiroyuki Akiba and Hiroaki Suzuki and Takao Aoki",

year = "1986",

month = dec,

day = "1",

language = "English",

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series = "Conference on Solid State Devices and Materials",

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T1 - P-WELL/N-WELL COMPATIBLE CMOS PROCESSING FOR ASIC APPLICATIONS.

AU - Kuroda, Tadahiro

AU - Akiba, Hiroyuki

AU - Suzuki, Hiroaki

AU - Aoki, Takao

PY - 1986/12/1

Y1 - 1986/12/1

N2 - This paper describes p-well/n-well compatible CMOS device structure and processing for ASIC applications, together with a design methodology and a scaling scenario. Process optimization has been carried out with careful adjustment of impurity profiles. Equivalent characteristics have been realized in both processes in regard to transistor characteristics, speed performance and latch-up immunity. Scaling philosophy has also been established and its properties are demonstrated.

AB - This paper describes p-well/n-well compatible CMOS device structure and processing for ASIC applications, together with a design methodology and a scaling scenario. Process optimization has been carried out with careful adjustment of impurity profiles. Equivalent characteristics have been realized in both processes in regard to transistor characteristics, speed performance and latch-up immunity. Scaling philosophy has also been established and its properties are demonstrated.

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UR - http://www.scopus.com/inward/citedby.url?scp=0022863158&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0022863158

SN - 493081314X

T3 - Conference on Solid State Devices and Materials

SP - 57

EP - 60

BT - Conference on Solid State Devices and Materials

PB - Business Cent for Academic Soc Japan

ER -

P-WELL/N-WELL COMPATIBLE CMOS PROCESSING FOR ASIC APPLICATIONS.

Abstract

Publication series

ASJC Scopus subject areas

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Cite this