This paper describes p-well/n-well compatible CMOS device structure and processing for ASIC applications, together with a design methodology and a scaling scenario. Process optimization has been carried out with careful adjustment of impurity profiles. Equivalent characteristics have been realized in both processes in regard to transistor characteristics, speed performance and latch-up immunity. Scaling philosophy has also been established and its properties are demonstrated.
|Title of host publication||Conference on Solid State Devices and Materials|
|Publisher||Business Cent for Academic Soc Japan|
|Number of pages||4|
|Publication status||Published - 1986 Dec 1|
|Name||Conference on Solid State Devices and Materials|
ASJC Scopus subject areas