Performance analysis of fully-adaptable CRC accelerators on an FPGA

Amila Akagic, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.

Original languageEnglish
Title of host publicationProceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Pages575-578
Number of pages4
DOIs
Publication statusPublished - 2012
Event22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway
Duration: 2012 Aug 292012 Aug 31

Other

Other22nd International Conference on Field Programmable Logic and Applications, FPL 2012
CountryNorway
CityOslo
Period12/8/2912/8/31

Fingerprint

Particle accelerators
Redundancy
Field programmable gate arrays (FPGA)
Throughput

ASJC Scopus subject areas

  • Computer Science Applications

Cite this

Akagic, A., & Amano, H. (2012). Performance analysis of fully-adaptable CRC accelerators on an FPGA. In Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 (pp. 575-578). [6339374] https://doi.org/10.1109/FPL.2012.6339374

Performance analysis of fully-adaptable CRC accelerators on an FPGA. / Akagic, Amila; Amano, Hideharu.

Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 575-578 6339374.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Akagic, A & Amano, H 2012, Performance analysis of fully-adaptable CRC accelerators on an FPGA. in Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012., 6339374, pp. 575-578, 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, Oslo, Norway, 12/8/29. https://doi.org/10.1109/FPL.2012.6339374
Akagic A, Amano H. Performance analysis of fully-adaptable CRC accelerators on an FPGA. In Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 575-578. 6339374 https://doi.org/10.1109/FPL.2012.6339374
Akagic, Amila ; Amano, Hideharu. / Performance analysis of fully-adaptable CRC accelerators on an FPGA. Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. pp. 575-578
@inproceedings{f43de66e22764ac0a900f48490d1031f,
title = "Performance analysis of fully-adaptable CRC accelerators on an FPGA",
abstract = "We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2{\%} area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14{\%} of area for 418.8Gbps without BRAM.",
author = "Amila Akagic and Hideharu Amano",
year = "2012",
doi = "10.1109/FPL.2012.6339374",
language = "English",
isbn = "9781467322560",
pages = "575--578",
booktitle = "Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012",

}

TY - GEN

T1 - Performance analysis of fully-adaptable CRC accelerators on an FPGA

AU - Akagic, Amila

AU - Amano, Hideharu

PY - 2012

Y1 - 2012

N2 - We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.

AB - We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.

UR - http://www.scopus.com/inward/record.url?scp=84870711639&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84870711639&partnerID=8YFLogxK

U2 - 10.1109/FPL.2012.6339374

DO - 10.1109/FPL.2012.6339374

M3 - Conference contribution

AN - SCOPUS:84870711639

SN - 9781467322560

SP - 575

EP - 578

BT - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

ER -