Abstract
We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 |
| Pages | 575-578 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway Duration: 2012 Aug 29 → 2012 Aug 31 |
Other
| Other | 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 |
|---|---|
| Country | Norway |
| City | Oslo |
| Period | 12/8/29 → 12/8/31 |
Fingerprint
ASJC Scopus subject areas
- Computer Science Applications
Cite this
Performance analysis of fully-adaptable CRC accelerators on an FPGA. / Akagic, Amila; Amano, Hideharu.
Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 575-578 6339374.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Performance analysis of fully-adaptable CRC accelerators on an FPGA
AU - Akagic, Amila
AU - Amano, Hideharu
PY - 2012
Y1 - 2012
N2 - We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.
AB - We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.
UR - http://www.scopus.com/inward/record.url?scp=84870711639&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84870711639&partnerID=8YFLogxK
U2 - 10.1109/FPL.2012.6339374
DO - 10.1109/FPL.2012.6339374
M3 - Conference contribution
AN - SCOPUS:84870711639
SN - 9781467322560
SP - 575
EP - 578
BT - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
ER -