Performance analysis of fully-adaptable CRC accelerators on an FPGA

Amila Akagic, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.

Original languageEnglish
Title of host publicationProceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Pages575-578
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 12
Event22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway
Duration: 2012 Aug 292012 Aug 31

Publication series

NameProceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Other

Other22nd International Conference on Field Programmable Logic and Applications, FPL 2012
CountryNorway
CityOslo
Period12/8/2912/8/31

ASJC Scopus subject areas

  • Computer Science Applications

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