Performance analysis of input and output queuing ATM switch with two speedup factors

Masaki Bandai, Masaki Umayabashi, Shigeki Shiokawa, Iwao Sasase

Research output: Contribution to journalArticle

Abstract

Recently, to handle large amounts of information more rapidly and reliably, the role of ATM switches in networks has become important. The conventional input and output queuing ATM switch model with a large speedup factor can achieve superior delay reduction performance. However, because of overflow in the output buffer, the cell loss probability is large. In this paper, to decrease cell loss probability, an input and output queuing ATM switch model with two speedup factors is proposed. In the proposed model, a large speedup factor is basically used, although a small speedup factor is adopted when the output queue length exceeds a threshold in the previous time slot. We evaluate the mean waiting time and cell loss probability by theoretical analysis and computer simulations. We show that the proposed model is useful in decreasing the cell loss probability without increasing the mean waiting time excessively.

Original languageEnglish
Pages (from-to)20-28
Number of pages9
JournalElectronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume82
Issue number10
DOIs
Publication statusPublished - 1999 Oct

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Automatic teller machines
Switches
Computer simulation

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Performance analysis of input and output queuing ATM switch with two speedup factors. / Bandai, Masaki; Umayabashi, Masaki; Shiokawa, Shigeki; Sasase, Iwao.

In: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi), Vol. 82, No. 10, 10.1999, p. 20-28.

Research output: Contribution to journalArticle

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