Abstract
Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.
| Original language | English |
|---|---|
| Title of host publication | 20th International Parallel and Distributed Processing Symposium, IPDPS 2006 |
| Volume | 2006 |
| DOIs | |
| Publication status | Published - 2006 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. / Hasegawa, Yohei; Abe, Shohei; Kurotaki, Shunsuke; Tuan, Vu Manh; Katsura, Naohiro; Nakamura, Takuro; Nishimura, Takashi; Amano, Hideharu.
20th International Parallel and Distributed Processing Symposium, IPDPS 2006. Vol. 2006 2006. 1639431.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor
AU - Hasegawa, Yohei
AU - Abe, Shohei
AU - Kurotaki, Shunsuke
AU - Tuan, Vu Manh
AU - Katsura, Naohiro
AU - Nakamura, Takuro
AU - Nishimura, Takashi
AU - Amano, Hideharu
PY - 2006
Y1 - 2006
N2 - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.
AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.
UR - http://www.scopus.com/inward/record.url?scp=33847103260&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33847103260&partnerID=8YFLogxK
U2 - 10.1109/IPDPS.2006.1639431
DO - 10.1109/IPDPS.2006.1639431
M3 - Conference contribution
AN - SCOPUS:33847103260
SN - 1424400546
SN - 9781424400546
VL - 2006
BT - 20th International Parallel and Distributed Processing Symposium, IPDPS 2006
ER -