Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Yohei Hasegawa; Shohei Abe; Shunsuke Kurotaki; Vu Manh Tuan; Naohiro Katsura; Takuro Nakamura; Takashi Nishimura; Hideharu Amano

doi:10.1109/IPDPS.2006.1639431

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

Original language	English
Title of host publication	20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Publisher	IEEE Computer Society
ISBN (Print)	1424400546, 9781424400546
DOIs	https://doi.org/10.1109/IPDPS.2006.1639431
Publication status	Published - 2006
Event	20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006 - Rhodes Island, Greece Duration: 2006 Apr 25 → 2006 Apr 29

Publication series

Name	20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Volume	2006

Conference

Conference	20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006
Country/Territory	Greece
City	Rhodes Island
Period	06/4/25 → 06/4/29

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/IPDPS.2006.1639431

Cite this

Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T., & Amano, H. (2006). Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006 [1639431] (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; Vol. 2006). IEEE Computer Society. https://doi.org/10.1109/IPDPS.2006.1639431

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. / Hasegawa, Yohei; Abe, Shohei; Kurotaki, Shunsuke et al.

20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 2006. 1639431 (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hasegawa, Y, Abe, S, Kurotaki, S, Tuan, VM, Katsura, N, Nakamura, T, Nishimura, T & Amano, H 2006, Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. in 20th International Parallel and Distributed Processing Symposium, IPDPS 2006., 1639431, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006, vol. 2006, IEEE Computer Society, 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006, Rhodes Island, Greece, 06/4/25. https://doi.org/10.1109/IPDPS.2006.1639431

Hasegawa Y, Abe S, Kurotaki S, Tuan VM, Katsura N, Nakamura T et al. Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society. 2006. 1639431. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006). https://doi.org/10.1109/IPDPS.2006.1639431

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abstract = "Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.",

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AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

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Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

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