Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

Original languageEnglish
Title of host publication20th International Parallel and Distributed Processing Symposium, IPDPS 2006
PublisherIEEE Computer Society
ISBN (Print)1424400546, 9781424400546
DOIs
Publication statusPublished - 2006 Jan 1
Event20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006 - Rhodes Island, Greece
Duration: 2006 Apr 252006 Apr 29

Publication series

Name20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Volume2006

Conference

Conference20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006
CountryGreece
CityRhodes Island
Period06/4/2506/4/29

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor'. Together they form a unique fingerprint.

  • Cite this

    Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T., & Amano, H. (2006). Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. In 20th International Parallel and Distributed Processing Symposium, IPDPS 2006 [1639431] (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; Vol. 2006). IEEE Computer Society. https://doi.org/10.1109/IPDPS.2006.1639431