Performance, cost, and energy evaluation of fat H-tree

A cost-efficient tree-based on-chip network

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

Fat H-Tree is a novel tree-based interconnection network providing a torus structure, which is formed by combining two folded H-Tree networks, and is an attractive alternative to tree-based networks such as Fat Trees in a microarchitecture domain. In this paper, we introduce Fat H-Tree and its deadlock-free routing algorithms. The performance of Fat H-Tree is evaluated using real application traces, and the result is compared with those of other tree-based networks. The network logic area and wire resources for Fat H-Tree are computed based on a typical implementation of on-chip routers using a 0.18μm standard cell library. In addition, the energy consumption is estimated based on the gate-level power analysis. The results show that 1) Fat H-Tree outperforms Fat Tree with two upward and four downward connections in terms of throughput and average hop count; 2) Fat H-Tree requires 19.3%-26.4% smaller network logic area compared with the Fat Tree; 3) Fat H-Tree consumes 8.3%-8.6% less energy compared with the Fat Tree due to its short average hop count; 4) Fat H-Tree uses slightly more wire resources compared with the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat H-Tree based on-chip networks.

Original languageEnglish
Title of host publicationProceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM
DOIs
Publication statusPublished - 2007
Event21st International Parallel and Distributed Processing Symposium, IPDPS 2007 - Long Beach, CA, United States
Duration: 2007 Mar 262007 Mar 30

Other

Other21st International Parallel and Distributed Processing Symposium, IPDPS 2007
CountryUnited States
CityLong Beach, CA
Period07/3/2607/3/30

Fingerprint

Oils and fats
Evaluation
Costs
Energy
Wire
Network on chip
Network-on-chip
Resources
Count
Logic
Routing algorithms
Tree Networks
Power Analysis
Routers
Interconnection Networks
Deadlock
Routing Algorithm
Router
Energy utilization
Energy Consumption

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Mathematics(all)

Cite this

Matsutani, H., Koibuchi, M., & Amano, H. (2007). Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network. In Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM [4227999] https://doi.org/10.1109/IPDPS.2007.370271

Performance, cost, and energy evaluation of fat H-tree : A cost-efficient tree-based on-chip network. / Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 2007. 4227999.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsutani, H, Koibuchi, M & Amano, H 2007, Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network. in Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM., 4227999, 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, United States, 07/3/26. https://doi.org/10.1109/IPDPS.2007.370271
Matsutani H, Koibuchi M, Amano H. Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network. In Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 2007. 4227999 https://doi.org/10.1109/IPDPS.2007.370271
Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu. / Performance, cost, and energy evaluation of fat H-tree : A cost-efficient tree-based on-chip network. Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 2007.
@inproceedings{990ae05286dd4e0eaa489f83c6900868,
title = "Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network",
abstract = "Fat H-Tree is a novel tree-based interconnection network providing a torus structure, which is formed by combining two folded H-Tree networks, and is an attractive alternative to tree-based networks such as Fat Trees in a microarchitecture domain. In this paper, we introduce Fat H-Tree and its deadlock-free routing algorithms. The performance of Fat H-Tree is evaluated using real application traces, and the result is compared with those of other tree-based networks. The network logic area and wire resources for Fat H-Tree are computed based on a typical implementation of on-chip routers using a 0.18μm standard cell library. In addition, the energy consumption is estimated based on the gate-level power analysis. The results show that 1) Fat H-Tree outperforms Fat Tree with two upward and four downward connections in terms of throughput and average hop count; 2) Fat H-Tree requires 19.3{\%}-26.4{\%} smaller network logic area compared with the Fat Tree; 3) Fat H-Tree consumes 8.3{\%}-8.6{\%} less energy compared with the Fat Tree due to its short average hop count; 4) Fat H-Tree uses slightly more wire resources compared with the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat H-Tree based on-chip networks.",
author = "Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano",
year = "2007",
doi = "10.1109/IPDPS.2007.370271",
language = "English",
isbn = "1424409101",
booktitle = "Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM",

}

TY - GEN

T1 - Performance, cost, and energy evaluation of fat H-tree

T2 - A cost-efficient tree-based on-chip network

AU - Matsutani, Hiroki

AU - Koibuchi, Michihiro

AU - Amano, Hideharu

PY - 2007

Y1 - 2007

N2 - Fat H-Tree is a novel tree-based interconnection network providing a torus structure, which is formed by combining two folded H-Tree networks, and is an attractive alternative to tree-based networks such as Fat Trees in a microarchitecture domain. In this paper, we introduce Fat H-Tree and its deadlock-free routing algorithms. The performance of Fat H-Tree is evaluated using real application traces, and the result is compared with those of other tree-based networks. The network logic area and wire resources for Fat H-Tree are computed based on a typical implementation of on-chip routers using a 0.18μm standard cell library. In addition, the energy consumption is estimated based on the gate-level power analysis. The results show that 1) Fat H-Tree outperforms Fat Tree with two upward and four downward connections in terms of throughput and average hop count; 2) Fat H-Tree requires 19.3%-26.4% smaller network logic area compared with the Fat Tree; 3) Fat H-Tree consumes 8.3%-8.6% less energy compared with the Fat Tree due to its short average hop count; 4) Fat H-Tree uses slightly more wire resources compared with the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat H-Tree based on-chip networks.

AB - Fat H-Tree is a novel tree-based interconnection network providing a torus structure, which is formed by combining two folded H-Tree networks, and is an attractive alternative to tree-based networks such as Fat Trees in a microarchitecture domain. In this paper, we introduce Fat H-Tree and its deadlock-free routing algorithms. The performance of Fat H-Tree is evaluated using real application traces, and the result is compared with those of other tree-based networks. The network logic area and wire resources for Fat H-Tree are computed based on a typical implementation of on-chip routers using a 0.18μm standard cell library. In addition, the energy consumption is estimated based on the gate-level power analysis. The results show that 1) Fat H-Tree outperforms Fat Tree with two upward and four downward connections in terms of throughput and average hop count; 2) Fat H-Tree requires 19.3%-26.4% smaller network logic area compared with the Fat Tree; 3) Fat H-Tree consumes 8.3%-8.6% less energy compared with the Fat Tree due to its short average hop count; 4) Fat H-Tree uses slightly more wire resources compared with the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat H-Tree based on-chip networks.

UR - http://www.scopus.com/inward/record.url?scp=34548760138&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548760138&partnerID=8YFLogxK

U2 - 10.1109/IPDPS.2007.370271

DO - 10.1109/IPDPS.2007.370271

M3 - Conference contribution

SN - 1424409101

SN - 9781424409105

BT - Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

ER -