Performance, cost, and power evaluations of on-chip network topologies in FPGAs

Sen In, Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

On-chip interconnection network has been used to connect a large number of modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance, cost, and power consumption of the system, and various network topologies have been proposed so far. To reveal cost- and powerefficient on-chip network structure in the reconfigurable systems, in this paper, we first estimate the performance of 2D-mesh, 2D-torus, Fat-Trees, Spidergon, Concentrated mesh, and Flattened Butterfly by using a network simulator. Then, these topologies are synthesized, placed, and routed by using the Xilinx ISE in order to show the number of slices required and power consumption for each topology. Based on the evaluation results, the performanceper- cost and the performance-per-power of these network topologies are compared. We discuss the pros and cons of the high-radix topologies, such as Concentrated mesh and Flattened Butterfly, when they are used in FPGAs. We also show that the high radix topologies are suitable to FPGAs, because of their relatively small area overhead and short hop count.

Original languageEnglish
Title of host publicationProceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
Pages181-189
Number of pages9
Publication statusPublished - 2010
Event9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 - Innsbruck, Austria
Duration: 2010 Feb 162010 Feb 18

Other

Other9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
CountryAustria
CityInnsbruck
Period10/2/1610/2/18

Fingerprint

Field programmable gate arrays (FPGA)
Topology
Costs
Electric power utilization
Network-on-chip
Oils and fats
Simulators

Keywords

  • Concentrated mesh
  • Fat-tree
  • FPGA
  • K-ary n-cube
  • Network-on-chip
  • Spidergon
  • Topology

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Software

Cite this

In, S., Matsutani, H., Koibuchi, M., Wang, D., & Amano, H. (2010). Performance, cost, and power evaluations of on-chip network topologies in FPGAs. In Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 (pp. 181-189)

Performance, cost, and power evaluations of on-chip network topologies in FPGAs. / In, Sen; Matsutani, Hiroki; Koibuchi, Michihiro; Wang, Daihan; Amano, Hideharu.

Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. 2010. p. 181-189.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

In, S, Matsutani, H, Koibuchi, M, Wang, D & Amano, H 2010, Performance, cost, and power evaluations of on-chip network topologies in FPGAs. in Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. pp. 181-189, 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010, Innsbruck, Austria, 10/2/16.
In S, Matsutani H, Koibuchi M, Wang D, Amano H. Performance, cost, and power evaluations of on-chip network topologies in FPGAs. In Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. 2010. p. 181-189
In, Sen ; Matsutani, Hiroki ; Koibuchi, Michihiro ; Wang, Daihan ; Amano, Hideharu. / Performance, cost, and power evaluations of on-chip network topologies in FPGAs. Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. 2010. pp. 181-189
@inproceedings{facaf34afe884d9f88fd3a635efe4bb7,
title = "Performance, cost, and power evaluations of on-chip network topologies in FPGAs",
abstract = "On-chip interconnection network has been used to connect a large number of modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance, cost, and power consumption of the system, and various network topologies have been proposed so far. To reveal cost- and powerefficient on-chip network structure in the reconfigurable systems, in this paper, we first estimate the performance of 2D-mesh, 2D-torus, Fat-Trees, Spidergon, Concentrated mesh, and Flattened Butterfly by using a network simulator. Then, these topologies are synthesized, placed, and routed by using the Xilinx ISE in order to show the number of slices required and power consumption for each topology. Based on the evaluation results, the performanceper- cost and the performance-per-power of these network topologies are compared. We discuss the pros and cons of the high-radix topologies, such as Concentrated mesh and Flattened Butterfly, when they are used in FPGAs. We also show that the high radix topologies are suitable to FPGAs, because of their relatively small area overhead and short hop count.",
keywords = "Concentrated mesh, Fat-tree, FPGA, K-ary n-cube, Network-on-chip, Spidergon, Topology",
author = "Sen In and Hiroki Matsutani and Michihiro Koibuchi and Daihan Wang and Hideharu Amano",
year = "2010",
language = "English",
isbn = "9780889868205",
pages = "181--189",
booktitle = "Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010",

}

TY - GEN

T1 - Performance, cost, and power evaluations of on-chip network topologies in FPGAs

AU - In, Sen

AU - Matsutani, Hiroki

AU - Koibuchi, Michihiro

AU - Wang, Daihan

AU - Amano, Hideharu

PY - 2010

Y1 - 2010

N2 - On-chip interconnection network has been used to connect a large number of modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance, cost, and power consumption of the system, and various network topologies have been proposed so far. To reveal cost- and powerefficient on-chip network structure in the reconfigurable systems, in this paper, we first estimate the performance of 2D-mesh, 2D-torus, Fat-Trees, Spidergon, Concentrated mesh, and Flattened Butterfly by using a network simulator. Then, these topologies are synthesized, placed, and routed by using the Xilinx ISE in order to show the number of slices required and power consumption for each topology. Based on the evaluation results, the performanceper- cost and the performance-per-power of these network topologies are compared. We discuss the pros and cons of the high-radix topologies, such as Concentrated mesh and Flattened Butterfly, when they are used in FPGAs. We also show that the high radix topologies are suitable to FPGAs, because of their relatively small area overhead and short hop count.

AB - On-chip interconnection network has been used to connect a large number of modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance, cost, and power consumption of the system, and various network topologies have been proposed so far. To reveal cost- and powerefficient on-chip network structure in the reconfigurable systems, in this paper, we first estimate the performance of 2D-mesh, 2D-torus, Fat-Trees, Spidergon, Concentrated mesh, and Flattened Butterfly by using a network simulator. Then, these topologies are synthesized, placed, and routed by using the Xilinx ISE in order to show the number of slices required and power consumption for each topology. Based on the evaluation results, the performanceper- cost and the performance-per-power of these network topologies are compared. We discuss the pros and cons of the high-radix topologies, such as Concentrated mesh and Flattened Butterfly, when they are used in FPGAs. We also show that the high radix topologies are suitable to FPGAs, because of their relatively small area overhead and short hop count.

KW - Concentrated mesh

KW - Fat-tree

KW - FPGA

KW - K-ary n-cube

KW - Network-on-chip

KW - Spidergon

KW - Topology

UR - http://www.scopus.com/inward/record.url?scp=77954612661&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77954612661&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:77954612661

SN - 9780889868205

SP - 181

EP - 189

BT - Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010

ER -