Performance, cost, and power evaluations of on-chip network topologies in FPGAs

Sen In, Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

On-chip interconnection network has been used to connect a large number of modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance, cost, and power consumption of the system, and various network topologies have been proposed so far. To reveal cost- and powerefficient on-chip network structure in the reconfigurable systems, in this paper, we first estimate the performance of 2D-mesh, 2D-torus, Fat-Trees, Spidergon, Concentrated mesh, and Flattened Butterfly by using a network simulator. Then, these topologies are synthesized, placed, and routed by using the Xilinx ISE in order to show the number of slices required and power consumption for each topology. Based on the evaluation results, the performanceper- cost and the performance-per-power of these network topologies are compared. We discuss the pros and cons of the high-radix topologies, such as Concentrated mesh and Flattened Butterfly, when they are used in FPGAs. We also show that the high radix topologies are suitable to FPGAs, because of their relatively small area overhead and short hop count.

Original languageEnglish
Title of host publicationProceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
Pages181-189
Number of pages9
Publication statusPublished - 2010 Jul 20
Event9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 - Innsbruck, Austria
Duration: 2010 Feb 162010 Feb 18

Publication series

NameProceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010

Other

Other9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
CountryAustria
CityInnsbruck
Period10/2/1610/2/18

Keywords

  • Concentrated mesh
  • FPGA
  • Fat-tree
  • K-ary n-cube
  • Network-on-chip
  • Spidergon
  • Topology

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Software

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  • Cite this

    In, S., Matsutani, H., Koibuchi, M., Wang, D., & Amano, H. (2010). Performance, cost, and power evaluations of on-chip network topologies in FPGAs. In Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 (pp. 181-189). (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).