Performance degradation by deactivated cores in 2-D mesh NoCs

Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Chip MultiProcessors (CMPs) will have dark silicon or frequently deactivated areas in a chip, as technology continues to scale down, due to power dissipation. In this work we estimate the influences of deactivated cores on performance of network-on-chips (NoCs). Even when a chip has a two-dimensional mesh topology, a deactivated core that includes an on-chip router makes topology irregular. We thus assume that a topology-agnostic deadlock-free routing is used with a moderate number of virtual channels in such CMPs. Thorough cycle-accurate network simulations of a 2-D mesh NoC, we found that (1) indeed a deactivated core degrades the performance to some extent in terms of throughput, but (2) latency is not increased or even reduced when a deactivated core is located in the corner of a mesh. Hence, we recommend choosing a corner core for deactivation to maintain the performance of NoCs.

Original languageEnglish
Title of host publicationProceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
PublisherIEEE Computer Society
Pages25-30
Number of pages6
ISBN (Print)9780768550862
DOIs
Publication statusPublished - 2013
Event2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 - Tokyo, Japan
Duration: 2013 Sep 262013 Sep 28

Other

Other2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
CountryJapan
CityTokyo
Period13/9/2613/9/28

Fingerprint

Topology
Degradation
Routers
Energy dissipation
Throughput
Silicon
Network-on-chip

Keywords

  • Darksilicon
  • Network-on-Chip
  • Systems on chip

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Fujiwara, I., Koibuchi, M., & Matsutani, H. (2013). Performance degradation by deactivated cores in 2-D mesh NoCs. In Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 (pp. 25-30). [6657899] IEEE Computer Society. https://doi.org/10.1109/MCSoC.2013.13

Performance degradation by deactivated cores in 2-D mesh NoCs. / Fujiwara, Ikki; Koibuchi, Michihiro; Matsutani, Hiroki.

Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013. IEEE Computer Society, 2013. p. 25-30 6657899.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fujiwara, I, Koibuchi, M & Matsutani, H 2013, Performance degradation by deactivated cores in 2-D mesh NoCs. in Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013., 6657899, IEEE Computer Society, pp. 25-30, 2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013, Tokyo, Japan, 13/9/26. https://doi.org/10.1109/MCSoC.2013.13
Fujiwara I, Koibuchi M, Matsutani H. Performance degradation by deactivated cores in 2-D mesh NoCs. In Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013. IEEE Computer Society. 2013. p. 25-30. 6657899 https://doi.org/10.1109/MCSoC.2013.13
Fujiwara, Ikki ; Koibuchi, Michihiro ; Matsutani, Hiroki. / Performance degradation by deactivated cores in 2-D mesh NoCs. Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013. IEEE Computer Society, 2013. pp. 25-30
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