Performance Evaluation of Instruction Set Architecture of MBP-Light in JUMP-1

Noriaki Suzuki, Hideharu Amano

Research output: Contribution to journalArticle

Abstract

The instruction set architecture of MBP-light, a dedicated processor for the DSM (Distributed Shared Memory) management of JUMP-1 is analyzed with a real prototype. The Buffer-Register Architecture proposed for MBP-core improves performance with 5.64% in the home cluster and 6.27% in a remote cluster. Only a special instruction for hashing cluster address is efficient and improves the performance with 2.80%, but other special instructions are almost useless. It appears that the dominant operations in the DSM management program were handling packet queues assigned into the local cluster. Thus, common RISC instructions, especially load/store instructions, are frequently used. Separating instruction and data memory improves performance with 33%. The results suggest that another alternative which provides separate on-chip cache and instructions dedicated for packet queue management is advantageous.

Original languageEnglish
Pages (from-to)1996-2005
Number of pages10
JournalIEICE Transactions on Information and Systems
VolumeE86-D
Issue number10
Publication statusPublished - 2003 Oct

Keywords

  • CC-NUMA
  • DSM management
  • Instruction set architecture

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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