Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA

Amila Akagić, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A compact architecture of five CRC algorithms based on multiple lookup tables approach is proposed. The focus of this paper is the tradeoff between implementation by using distributed LUTs or BRAM. Our results show that BRAM-based approach is more efficient in terms of area utilization, but LUT based approach allows higher throughput. The proposed architecture has been implemented on Xilinx Virtex 6 LX195T prototyping device, requiring less than 1% of the device resources. Experimental results show that throughput doubles when number of processed bits is doubled. Maximum achieved throughput is 170 Gbps for processing 512 bits at a time with LUT-based approach. We show that in terms of achievable clock speed BRAM-based approach is more efficient when processing 32, 64 and 128 bits at a time, while higher throughput is achieved by LUT-based approach for algorithms that process 256 and 512 bits at a time. In terms of hardware cost, BRAM-based approach without register balancing optimization proved to be most efficient solution.

Original languageEnglish
Title of host publicationProceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011
Pages164-169
Number of pages6
DOIs
Publication statusPublished - 2011
Event2011 1st International Symposium on Access Spaces, ISAS 2011 - Yokohama, Japan
Duration: 2011 Jun 172011 Jun 19

Other

Other2011 1st International Symposium on Access Spaces, ISAS 2011
CountryJapan
CityYokohama
Period11/6/1711/6/19

Fingerprint

Table lookup
Field programmable gate arrays (FPGA)
Throughput
Processing
Clocks
Hardware
Costs

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Akagić, A., & Amano, H. (2011). Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA. In Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011 (pp. 164-169). [5960941] https://doi.org/10.1109/ISAS.2011.5960941

Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA. / Akagić, Amila; Amano, Hideharu.

Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. 2011. p. 164-169 5960941.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Akagić, A & Amano, H 2011, Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA. in Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011., 5960941, pp. 164-169, 2011 1st International Symposium on Access Spaces, ISAS 2011, Yokohama, Japan, 11/6/17. https://doi.org/10.1109/ISAS.2011.5960941
Akagić A, Amano H. Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA. In Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. 2011. p. 164-169. 5960941 https://doi.org/10.1109/ISAS.2011.5960941
Akagić, Amila ; Amano, Hideharu. / Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA. Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. 2011. pp. 164-169
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