Performance evaluation of SNAIL: A multiprocessor based on the Simple Serial Synchronized Multistage Interconnection Network architecture

Junji Yamamoto, Takashi Fujiwara, Takuji Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Simple Serial Synchronized (SSS)-Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called the SNAIL with the SSS-MIN are presented. The heart of SNAIL is a prototype 1 μm CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs at a 50 MHz clock speed. The message combining is implemented with only a 20% increase in hardware. From empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSS-MIN are tolerable, and the bandwidth of the SSS-MIN is sufficient.

Original languageEnglish
Pages (from-to)1081-1103
Number of pages23
JournalParallel Computing
Volume25
Issue number9
DOIs
Publication statusPublished - 1999 Sep

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Networks and Communications
  • Computer Graphics and Computer-Aided Design
  • Artificial Intelligence

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