Abstract
Simple Serial Synchronized (SSS)-Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called the SNAIL with the SSS-MIN are presented. The heart of SNAIL is a prototype 1 μm CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs at a 50 MHz clock speed. The message combining is implemented with only a 20% increase in hardware. From empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSS-MIN are tolerable, and the bandwidth of the SSS-MIN is sufficient.
| Original language | English |
|---|---|
| Pages (from-to) | 1081-1103 |
| Number of pages | 23 |
| Journal | Parallel Computing |
| Volume | 25 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 1999 Sep |
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ASJC Scopus subject areas
- Computer Science Applications
- Hardware and Architecture
- Control and Systems Engineering
Cite this
Performance evaluation of SNAIL : A multiprocessor based on the Simple Serial Synchronized Multistage Interconnection Network architecture. / Yamamoto, Junji; Fujiwara, Takashi; Komeda, Takuji; Kamei, Takayuki; Hanawa, Toshihiro; Amano, Hideharu.
In: Parallel Computing, Vol. 25, No. 9, 09.1999, p. 1081-1103.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Performance evaluation of SNAIL
T2 - A multiprocessor based on the Simple Serial Synchronized Multistage Interconnection Network architecture
AU - Yamamoto, Junji
AU - Fujiwara, Takashi
AU - Komeda, Takuji
AU - Kamei, Takayuki
AU - Hanawa, Toshihiro
AU - Amano, Hideharu
PY - 1999/9
Y1 - 1999/9
N2 - Simple Serial Synchronized (SSS)-Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called the SNAIL with the SSS-MIN are presented. The heart of SNAIL is a prototype 1 μm CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs at a 50 MHz clock speed. The message combining is implemented with only a 20% increase in hardware. From empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSS-MIN are tolerable, and the bandwidth of the SSS-MIN is sufficient.
AB - Simple Serial Synchronized (SSS)-Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called the SNAIL with the SSS-MIN are presented. The heart of SNAIL is a prototype 1 μm CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs at a 50 MHz clock speed. The message combining is implemented with only a 20% increase in hardware. From empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSS-MIN are tolerable, and the bandwidth of the SSS-MIN is sufficient.
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UR - http://www.scopus.com/inward/citedby.url?scp=0032643843&partnerID=8YFLogxK
U2 - 10.1016/S0167-8191(99)00038-1
DO - 10.1016/S0167-8191(99)00038-1
M3 - Article
AN - SCOPUS:0032643843
VL - 25
SP - 1081
EP - 1103
JO - Parallel Computing
JF - Parallel Computing
SN - 0167-8191
IS - 9
ER -