Performance evaluation on low-latency communication mechanism of DIMMnet-2

Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

By recent performance improvement of interconnection networks for PC cluster, a standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot. Although the current board is a prototype using an FPGA, using BOTF which is low latency PIO communication method, the bidirectional bandwidth reaches about 1087.56 MByte/s, and the minimum unidirectional latency is about 0.632 μs.

Original languageEnglish
Title of host publicationProceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems
Pages57-62
Number of pages6
Publication statusPublished - 2007
EventIASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007 - Innsbruck, Austria
Duration: 2007 Feb 132007 Feb 15

Other

OtherIASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007
CountryAustria
CityInnsbruck
Period07/2/1307/2/15

Fingerprint

Interfaces (computer)
Communication
Field programmable gate arrays (FPGA)
Bandwidth
Data storage equipment

Keywords

  • Interconnect
  • Memory slot
  • PC cluster

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

Cite this

Kitamura, A., Miyabe, Y., Miyashiro, T., Tanabe, N., Nakajo, H., & Amano, H. (2007). Performance evaluation on low-latency communication mechanism of DIMMnet-2. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems (pp. 57-62)

Performance evaluation on low-latency communication mechanism of DIMMnet-2. / Kitamura, Akira; Miyabe, Yasuo; Miyashiro, Tomotaka; Tanabe, Noboru; Nakajo, Hironori; Amano, Hideharu.

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. 2007. p. 57-62.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kitamura, A, Miyabe, Y, Miyashiro, T, Tanabe, N, Nakajo, H & Amano, H 2007, Performance evaluation on low-latency communication mechanism of DIMMnet-2. in Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. pp. 57-62, IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007, Innsbruck, Austria, 07/2/13.
Kitamura A, Miyabe Y, Miyashiro T, Tanabe N, Nakajo H, Amano H. Performance evaluation on low-latency communication mechanism of DIMMnet-2. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. 2007. p. 57-62
Kitamura, Akira ; Miyabe, Yasuo ; Miyashiro, Tomotaka ; Tanabe, Noboru ; Nakajo, Hironori ; Amano, Hideharu. / Performance evaluation on low-latency communication mechanism of DIMMnet-2. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. 2007. pp. 57-62
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