Performance evaluation on low-latency communication mechanism of DIMMnet-2

Akira Kitamura; Yasuo Miyabe; Tomotaka Miyashiro; Noboru Tanabe; Hironori Nakajo; Hideharu Amano

Performance evaluation on low-latency communication mechanism of DIMMnet-2

Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

By recent performance improvement of interconnection networks for PC cluster, a standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot. Although the current board is a prototype using an FPGA, using BOTF which is low latency PIO communication method, the bidirectional bandwidth reaches about 1087.56 MByte/s, and the minimum unidirectional latency is about 0.632 μs.

Original language	English
Title of host publication	Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007
Pages	57-62
Number of pages	6
Publication status	Published - 2007 Dec 1
Event	IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007 - Innsbruck, Austria Duration: 2007 Feb 13 → 2007 Feb 15

Publication series

Name	Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems
ISSN (Print)	1027-2658

Other

Other	IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007
Country/Territory	Austria
City	Innsbruck
Period	07/2/13 → 07/2/15

Keywords

Interconnect
Memory slot
PC cluster

ASJC Scopus subject areas

Software
Hardware and Architecture
Computer Networks and Communications

Cite this

Kitamura, A., Miyabe, Y., Miyashiro, T., Tanabe, N., Nakajo, H., & Amano, H. (2007). Performance evaluation on low-latency communication mechanism of DIMMnet-2. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007 (pp. 57-62). (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Performance evaluation on low-latency communication mechanism of DIMMnet-2. / Kitamura, Akira; Miyabe, Yasuo; Miyashiro, Tomotaka et al.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007. 2007. p. 57-62 (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kitamura, A, Miyabe, Y, Miyashiro, T, Tanabe, N, Nakajo, H & Amano, H 2007, Performance evaluation on low-latency communication mechanism of DIMMnet-2. in Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, pp. 57-62, IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007, Innsbruck, Austria, 07/2/13.

Kitamura A, Miyabe Y, Miyashiro T, Tanabe N, Nakajo H, Amano H. Performance evaluation on low-latency communication mechanism of DIMMnet-2. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007. 2007. p. 57-62. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Kitamura, Akira ; Miyabe, Yasuo ; Miyashiro, Tomotaka et al. / Performance evaluation on low-latency communication mechanism of DIMMnet-2. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007. 2007. pp. 57-62 (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

@inproceedings{1cce803552294baabd4062ad17c04e4e,

title = "Performance evaluation on low-latency communication mechanism of DIMMnet-2",

abstract = "By recent performance improvement of interconnection networks for PC cluster, a standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot. Although the current board is a prototype using an FPGA, using BOTF which is low latency PIO communication method, the bidirectional bandwidth reaches about 1087.56 MByte/s, and the minimum unidirectional latency is about 0.632 μs.",

keywords = "Interconnect, Memory slot, PC cluster",

author = "Akira Kitamura and Yasuo Miyabe and Tomotaka Miyashiro and Noboru Tanabe and Hironori Nakajo and Hideharu Amano",

year = "2007",

month = dec,

day = "1",

language = "English",

isbn = "9780889866379",

series = "Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems",

pages = "57--62",

booktitle = "Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007",

note = "IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007 ; Conference date: 13-02-2007 Through 15-02-2007",

}

TY - GEN

T1 - Performance evaluation on low-latency communication mechanism of DIMMnet-2

AU - Kitamura, Akira

AU - Miyabe, Yasuo

AU - Miyashiro, Tomotaka

AU - Tanabe, Noboru

AU - Nakajo, Hironori

AU - Amano, Hideharu

PY - 2007/12/1

Y1 - 2007/12/1

N2 - By recent performance improvement of interconnection networks for PC cluster, a standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot. Although the current board is a prototype using an FPGA, using BOTF which is low latency PIO communication method, the bidirectional bandwidth reaches about 1087.56 MByte/s, and the minimum unidirectional latency is about 0.632 μs.

AB - By recent performance improvement of interconnection networks for PC cluster, a standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot. Although the current board is a prototype using an FPGA, using BOTF which is low latency PIO communication method, the bidirectional bandwidth reaches about 1087.56 MByte/s, and the minimum unidirectional latency is about 0.632 μs.

KW - Interconnect

KW - Memory slot

KW - PC cluster

UR - http://www.scopus.com/inward/record.url?scp=56149096133&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=56149096133&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:56149096133

SN - 9780889866379

T3 - Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

SP - 57

EP - 62

BT - Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007

T2 - IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007

Y2 - 13 February 2007 through 15 February 2007

ER -

Performance evaluation on low-latency communication mechanism of DIMMnet-2

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this