Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs

Masumi Saitoh, Yukio Nakabayashi, Kensuke Ota, Ken Uchida, Toshinori Numata

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

Original languageEnglish
Article number6072236
Pages (from-to)8-10
Number of pages3
JournalIEEE Electron Device Letters
Volume33
Issue number1
DOIs
Publication statusPublished - 2012 Jan
Externally publishedYes

Fingerprint

Silicon
Nanowires
Transistors

Keywords

  • Mobility
  • nanowire transistor
  • parasitic resistance
  • stress memorization technique (SMT)
  • trigate

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs. / Saitoh, Masumi; Nakabayashi, Yukio; Ota, Kensuke; Uchida, Ken; Numata, Toshinori.

In: IEEE Electron Device Letters, Vol. 33, No. 1, 6072236, 01.2012, p. 8-10.

Research output: Contribution to journalArticle

Saitoh, Masumi ; Nakabayashi, Yukio ; Ota, Kensuke ; Uchida, Ken ; Numata, Toshinori. / Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs. In: IEEE Electron Device Letters. 2012 ; Vol. 33, No. 1. pp. 8-10.
@article{d48e396dd0b646c2847a7651793abfbb,
title = "Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs",
abstract = "We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.",
keywords = "Mobility, nanowire transistor, parasitic resistance, stress memorization technique (SMT), trigate",
author = "Masumi Saitoh and Yukio Nakabayashi and Kensuke Ota and Ken Uchida and Toshinori Numata",
year = "2012",
month = "1",
doi = "10.1109/LED.2011.2171315",
language = "English",
volume = "33",
pages = "8--10",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs

AU - Saitoh, Masumi

AU - Nakabayashi, Yukio

AU - Ota, Kensuke

AU - Uchida, Ken

AU - Numata, Toshinori

PY - 2012/1

Y1 - 2012/1

N2 - We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

AB - We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

KW - Mobility

KW - nanowire transistor

KW - parasitic resistance

KW - stress memorization technique (SMT)

KW - trigate

UR - http://www.scopus.com/inward/record.url?scp=84655161262&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84655161262&partnerID=8YFLogxK

U2 - 10.1109/LED.2011.2171315

DO - 10.1109/LED.2011.2171315

M3 - Article

VL - 33

SP - 8

EP - 10

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 1

M1 - 6072236

ER -