Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs

Masumi Saitoh, Yukio Nakabayashi, Kensuke Ota, Ken Uchida, Toshinori Numata

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

Original languageEnglish
Article number6072236
Pages (from-to)8-10
Number of pages3
JournalIEEE Electron Device Letters
Volume33
Issue number1
DOIs
Publication statusPublished - 2012 Jan 1

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Keywords

  • Mobility
  • nanowire transistor
  • parasitic resistance
  • stress memorization technique (SMT)
  • trigate

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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