Performance improvement methodology for ClearSpeed's CSX600

Yuri Nishikawa; Michihiro Koibuchi; Masato Yoshimi; Kenichi Miura; Hideharu Amano

doi:10.1109/ICPP.2007.66

Performance improvement methodology for ClearSpeed's CSX600

Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper focuses on a performance of network-on-a-chip (NoC) and I/O of ClearSpeed's CSX600 coprocessor with 96 multithread processing elements. Two versions of the Himeno Benchmark were implemented on the CSX600 to evaluate its performance when it encounters frequent memory transfers between shared and local memories, or between local memories. In order to efficiently use the NoC bandwidth, the dataflow was customized to the one-dimensional array structure of CSX600's NoC. The results of evaluation and profiling indicate that the performance was lower than 1/50 of the sustained performance. We show three key points to improve the performance on such a case: 1) exploiting bandwidth between mono and poly memory, 2) further program tuning, and 3) architectural reform.

Original language	English
Title of host publication	2007 International Conference on Parallel Processing, ICPP
DOIs	https://doi.org/10.1109/ICPP.2007.66
Publication status	Published - 2007 Dec 1
Event	36th International Conference on Parallel Processing in Xi'an, ICPP - Xi'an, China Duration: 2007 Sept 10 → 2007 Sept 14

Publication series

Name	Proceedings of the International Conference on Parallel Processing
ISSN (Print)	0190-3918

Other

Other	36th International Conference on Parallel Processing in Xi'an, ICPP
Country/Territory	China
City	Xi'an
Period	07/9/10 → 07/9/14

ASJC Scopus subject areas

Hardware and Architecture
Engineering(all)

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10.1109/ICPP.2007.66

Cite this

Nishikawa, Y, Koibuchi, M, Yoshimi, M, Miura, K & Amano, H 2007, Performance improvement methodology for ClearSpeed's CSX600. in 2007 International Conference on Parallel Processing, ICPP., 4343884, Proceedings of the International Conference on Parallel Processing, 36th International Conference on Parallel Processing in Xi'an, ICPP, Xi'an, China, 07/9/10. https://doi.org/10.1109/ICPP.2007.66

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title = "Performance improvement methodology for ClearSpeed's CSX600",

abstract = "This paper focuses on a performance of network-on-a-chip (NoC) and I/O of ClearSpeed's CSX600 coprocessor with 96 multithread processing elements. Two versions of the Himeno Benchmark were implemented on the CSX600 to evaluate its performance when it encounters frequent memory transfers between shared and local memories, or between local memories. In order to efficiently use the NoC bandwidth, the dataflow was customized to the one-dimensional array structure of CSX600's NoC. The results of evaluation and profiling indicate that the performance was lower than 1/50 of the sustained performance. We show three key points to improve the performance on such a case: 1) exploiting bandwidth between mono and poly memory, 2) further program tuning, and 3) architectural reform.",

author = "Yuri Nishikawa and Michihiro Koibuchi and Masato Yoshimi and Kenichi Miura and Hideharu Amano",

year = "2007",

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doi = "10.1109/ICPP.2007.66",

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AU - Nishikawa, Yuri

AU - Koibuchi, Michihiro

AU - Yoshimi, Masato

AU - Miura, Kenichi

AU - Amano, Hideharu

PY - 2007/12/1

Y1 - 2007/12/1

N2 - This paper focuses on a performance of network-on-a-chip (NoC) and I/O of ClearSpeed's CSX600 coprocessor with 96 multithread processing elements. Two versions of the Himeno Benchmark were implemented on the CSX600 to evaluate its performance when it encounters frequent memory transfers between shared and local memories, or between local memories. In order to efficiently use the NoC bandwidth, the dataflow was customized to the one-dimensional array structure of CSX600's NoC. The results of evaluation and profiling indicate that the performance was lower than 1/50 of the sustained performance. We show three key points to improve the performance on such a case: 1) exploiting bandwidth between mono and poly memory, 2) further program tuning, and 3) architectural reform.

AB - This paper focuses on a performance of network-on-a-chip (NoC) and I/O of ClearSpeed's CSX600 coprocessor with 96 multithread processing elements. Two versions of the Himeno Benchmark were implemented on the CSX600 to evaluate its performance when it encounters frequent memory transfers between shared and local memories, or between local memories. In order to efficiently use the NoC bandwidth, the dataflow was customized to the one-dimensional array structure of CSX600's NoC. The results of evaluation and profiling indicate that the performance was lower than 1/50 of the sustained performance. We show three key points to improve the performance on such a case: 1) exploiting bandwidth between mono and poly memory, 2) further program tuning, and 3) architectural reform.

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Performance improvement methodology for ClearSpeed's CSX600

Abstract

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