Performance improvement technique for synchronous circuits realized as LUT-based FPGA's

Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration; only the register location is altered. It improves clock speed and data throughput at the expense of latency. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., remapping, replacement, and rerouting, are unnecessary when improving circuit performance. After applying our technique to some benchmark circuits, the average performance improvement was 333% for six combination circuits, and 25% for 18 sequential circuits.

Original languageEnglish
Pages (from-to)455-459
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume3
Issue number3
DOIs
Publication statusPublished - 1995 Sep

Fingerprint

Field programmable gate arrays (FPGA)
Networks (circuits)
Sequential circuits
Clocks
Throughput

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Performance improvement technique for synchronous circuits realized as LUT-based FPGA's. / Miyazaki, Toshiaki; Nakada, Hiroshi; Tsutsui, Akihiro; Yamada, Kazuhisa; Ohta, Naohisa.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 3, 09.1995, p. 455-459.

Research output: Contribution to journalArticle

Miyazaki, Toshiaki ; Nakada, Hiroshi ; Tsutsui, Akihiro ; Yamada, Kazuhisa ; Ohta, Naohisa. / Performance improvement technique for synchronous circuits realized as LUT-based FPGA's. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1995 ; Vol. 3, No. 3. pp. 455-459.
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