Performance, variability and reliability of silicon tri-gate nanowire MOSFETs

Masumi Saitoh; Kensuke Ota; Chika Tanaka; Yukio Nakabayashi; Ken Uchida; Toshinori Numata

doi:10.1109/IRPS.2012.6241864

Performance, variability and reliability of silicon tri-gate nanowire MOSFETs

Masumi Saitoh, Kensuke Ota, Chika Tanaka, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (R _SD) reduction. <100>-oriented NW channel further improves on-current as compared to <110> NW channel. In Pelgrom plot of σV _th of NW Tr., there exists a universal line whose A _vt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σV _th universal line is eliminated by suppressing R _SD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.

Original language	English
Title of host publication	2012 IEEE International Reliability Physics Symposium, IRPS 2012
Pages	6A.3.1-6A.3.6
DOIs	https://doi.org/10.1109/IRPS.2012.6241864
Publication status	Published - 2012 Sep 28
Event	2012 IEEE International Reliability Physics Symposium, IRPS 2012 - Anaheim, CA, United States Duration: 2012 Apr 15 → 2012 Apr 19

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Other

Other	2012 IEEE International Reliability Physics Symposium, IRPS 2012
Country	United States
City	Anaheim, CA
Period	12/4/15 → 12/4/19

Keywords

nanowire
negative bias temperature instability
parasitic resistance
tri-gate
variability

ASJC Scopus subject areas

Engineering(all)

Access to Document

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Performance, variability and reliability of silicon tri-gate nanowire MOSFETs. / Saitoh, Masumi; Ota, Kensuke; Tanaka, Chika; Nakabayashi, Yukio; Uchida, Ken; Numata, Toshinori.

2012 IEEE International Reliability Physics Symposium, IRPS 2012. 2012. p. 6A.3.1-6A.3.6 6241864 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Saitoh, M, Ota, K, Tanaka, C, Nakabayashi, Y, Uchida, K & Numata, T 2012, Performance, variability and reliability of silicon tri-gate nanowire MOSFETs. in 2012 IEEE International Reliability Physics Symposium, IRPS 2012., 6241864, IEEE International Reliability Physics Symposium Proceedings, pp. 6A.3.1-6A.3.6, 2012 IEEE International Reliability Physics Symposium, IRPS 2012, Anaheim, CA, United States, 12/4/15. https://doi.org/10.1109/IRPS.2012.6241864

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abstract = "We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (R SD) reduction. <100>-oriented NW channel further improves on-current as compared to <110> NW channel. In Pelgrom plot of σV th of NW Tr., there exists a universal line whose A vt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σV th universal line is eliminated by suppressing R SD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.",

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