Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor

Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor with the capability of changing its hardware functionality within a clock cycle. While implementing an application on the DRP, designers face the task of selecting how to efficiently use resources in order to achieve particular goals such as to improve the performance, to reduce the power dissipation, or to minimize the resource use. To analyze the impact of trade-off selections on these aspects, the Discrete Cosine Transform (DCT) algorithm has been implemented exploiting various design policies. The evaluation result shows that the performance, cost and consuming power are influenced by the implementation method. For example, the execution time can reduce 17% in case of using the distributed memory against the register files; or up to 40% whether the embedded multipliers are used.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Pages115-121
Number of pages7
Volume3985 LNCS
Publication statusPublished - 2006
Event2nd International Workshop on Applied Reconfigurable Computing, ARC 2006 - Delft, United States
Duration: 2006 Mar 12006 Mar 3

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3985 LNCS
ISSN (Print)03029743
ISSN (Electronic)16113349

Other

Other2nd International Workshop on Applied Reconfigurable Computing, ARC 2006
CountryUnited States
CityDelft
Period06/3/106/3/3

Fingerprint

Discrete Cosine Transform
Discrete cosine transforms
Clocks
Energy dissipation
Electronic equipment
Trade-offs
Hardware
Data storage equipment
Costs and Cost Analysis
Evaluation
Costs
Resources
Distributed Memory
Execution Time
Multiplier
Dissipation
Electronics
Minimise
Cycle

ASJC Scopus subject areas

  • Computer Science(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Theoretical Computer Science

Cite this

Tuan, V. M., Hasegawa, Y., Katsura, N., & Amano, H. (2006). Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3985 LNCS, pp. 115-121). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3985 LNCS).

Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor. / Tuan, Vu Manh; Hasegawa, Yohei; Katsura, Naohiro; Amano, Hideharu.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 3985 LNCS 2006. p. 115-121 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3985 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tuan, VM, Hasegawa, Y, Katsura, N & Amano, H 2006, Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor. in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). vol. 3985 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 3985 LNCS, pp. 115-121, 2nd International Workshop on Applied Reconfigurable Computing, ARC 2006, Delft, United States, 06/3/1.
Tuan VM, Hasegawa Y, Katsura N, Amano H. Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 3985 LNCS. 2006. p. 115-121. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
Tuan, Vu Manh ; Hasegawa, Yohei ; Katsura, Naohiro ; Amano, Hideharu. / Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 3985 LNCS 2006. pp. 115-121 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
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