Perspective of low-power and high-speed wireless inter-chip communications for SiP integration

Tadahiro Kuroda, Noriyuki Miura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Performance gap between computation in a chip and communication between chips is widening. "System in a Package" (SiP) reduces chip distance significantly, enabling a high-speed and low-power interface. Electrical non-contact interfaces using inductive/capacitive coupling have advantages over mechanical interfaces employing Through Silicon Vias (TSV) and micro bumps. In this paper, a perspective of using wireless links between stacked chips in a package is presented. Techniques for high-speed and low-power data communications are discussed in various levels from signaling, circuit design, IC layout, and magnetic field design, as well as cross talk analysis and its countermeasures. A 1Tb/s 3W transceiver in 0.18μm CMOS is presented. Both clock and data are transmitted by inductive coupling. 1024 data transceivers are arranged with a pitch of 30μm. A 4-phases Time Division Multiple Access (TDMA) technique reduces crosstalk effectively. Measured Bit Error Rate (BER) is lower than 10-13. Bi-Phase Modulation (BPM) is employed to improve noise immunity, resulting in power reduction.

Original languageEnglish
Title of host publicationESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference
PublisherIEEE Computer Society
Pages3-6
Number of pages4
ISBN (Print)1424403014, 9781424403011
DOIs
Publication statusPublished - 2006
EventESSDERC 2006 - 36th European Solid-State Device Research Conference - Montreux, Switzerland
Duration: 2006 Sep 192006 Sep 21

Other

OtherESSDERC 2006 - 36th European Solid-State Device Research Conference
CountrySwitzerland
CityMontreux
Period06/9/1906/9/21

Fingerprint

Transceivers
Time division multiple access
Communication
Phase modulation
Silicon
Crosstalk
Bit error rate
Telecommunication links
Clocks
Magnetic fields
Networks (circuits)
Integrated circuit design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kuroda, T., & Miura, N. (2006). Perspective of low-power and high-speed wireless inter-chip communications for SiP integration. In ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference (pp. 3-6). [4099847] IEEE Computer Society. https://doi.org/10.1109/ESSDER.2006.307629

Perspective of low-power and high-speed wireless inter-chip communications for SiP integration. / Kuroda, Tadahiro; Miura, Noriyuki.

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference. IEEE Computer Society, 2006. p. 3-6 4099847.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kuroda, T & Miura, N 2006, Perspective of low-power and high-speed wireless inter-chip communications for SiP integration. in ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference., 4099847, IEEE Computer Society, pp. 3-6, ESSDERC 2006 - 36th European Solid-State Device Research Conference, Montreux, Switzerland, 06/9/19. https://doi.org/10.1109/ESSDER.2006.307629
Kuroda T, Miura N. Perspective of low-power and high-speed wireless inter-chip communications for SiP integration. In ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference. IEEE Computer Society. 2006. p. 3-6. 4099847 https://doi.org/10.1109/ESSDER.2006.307629
Kuroda, Tadahiro ; Miura, Noriyuki. / Perspective of low-power and high-speed wireless inter-chip communications for SiP integration. ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference. IEEE Computer Society, 2006. pp. 3-6
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