PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators

Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

PhaseMAC (PMAC), a phase domain Gated-Ring-Oscillator (GRO) based 8bit MAC circuit, is proposed to minimize both area and power consumption of deep learning accelerators. PMAC composes of only digital cells and consumes significantly smaller power than standard digital designs, owing to its efficient analog accumulation nature. It occupies 26.6 times smaller area than conventional analog designs, which is competitive to digital MAC circuits. PMAC achieves a peak efficiency of 14 TOPS/W, which is best reported and 48% higher than conventional arts. Results in anomaly detection tasks are demonstrated, which is the hottest application in the industrial IoT scene.

Original languageEnglish
Title of host publication2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages263-264
Number of pages2
ISBN (Electronic)9781538667002
DOIs
Publication statusPublished - 2018 Oct 22
Externally publishedYes
Event32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States
Duration: 2018 Jun 182018 Jun 22

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2018-June

Other

Other32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country/TerritoryUnited States
CityHonolulu
Period18/6/1818/6/22

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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