Physical understanding of Vth and Idsat variations in (110) CMOSFETs

Masumi Saitoh, Nobuaki Yasutake, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)

    Abstract

    In this paper, the first systematic study of Vth variations (σVth) and Idsat variations (σI dsat) in (110) n/pMOSFETs is presented. σVth in (110) n/pFETs with high channel dose are larger than (100) n/pFETs. It is found that the variations of B ion channeling, B-induced interface traps, and As-induced interface fixed charges enhance σVth in (110) n/pFETs. Steep B profile and moderate P doping into the surface are desirable to minimize σVth in (110) FETs. We also found that σI dsat is determined by both σVth and the degree of velocity saturation. σIdsat of scaled (110) CMOS can be lowered compared to (100) CMOS by the optimum channel impurity design.

    Original languageEnglish
    Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
    Pages114-115
    Number of pages2
    Publication statusPublished - 2009 Nov 16
    Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
    Duration: 2009 Jun 162009 Jun 18

    Publication series

    NameDigest of Technical Papers - Symposium on VLSI Technology
    ISSN (Print)0743-1562

    Other

    Other2009 Symposium on VLSI Technology, VLSIT 2009
    CountryJapan
    CityKyoto
    Period09/6/1609/6/18

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Saitoh, M., Yasutake, N., Nakabayashi, Y., Uchida, K., & Numata, T. (2009). Physical understanding of Vth and Idsat variations in (110) CMOSFETs. In 2009 Symposium on VLSI Technology, VLSIT 2009 (pp. 114-115). [5200654] (Digest of Technical Papers - Symposium on VLSI Technology).