Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth

Kazuei Hironaka, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A coarse grained dynamically reconfigurable processor (CGDRP) with both Dual Vdd and Dual Vth is proposed with power centric Dual Vdd and Dual Vth assignment policies. The evaluation result shows that the Vth and Vdd assignment optimization algorithm reduces 37% of total consuming power within keeping the operational frequency.

Original languageEnglish
Title of host publicationProceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011
Pages404-409
Number of pages6
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 - Cancun, Quintana Roo, Mexico
Duration: 2011 Nov 302011 Dec 2

Publication series

NameProceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

Other

Other2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011
CountryMexico
CityCancun, Quintana Roo
Period11/11/3011/12/2

Keywords

  • CGRA
  • DRPA
  • coarse grained dynamically reconfigurable device
  • reconfigurable device

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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    Hironaka, K., & Amano, H. (2011). Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth. In Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 (pp. 404-409). [6128611] (Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011). https://doi.org/10.1109/ReConFig.2011.70