Power reduction in high-speed inter-chip data communications

Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper describes power reduction techniques in high-speed inter-chip data communication with inductive coupled wireless interface for 30-stacked SiP. NRZ signaling where signal is not transmitted when data holds reduces power dissipation in proportion to switching activity. A low-power single-end transmitter is presented for 55% transmitter's power reduction. Depending on communication distance, transmit power is controlled for both power and crosstalk reduction. 195Gb/s, 1.2W high-speed and low-power interface with these techniques has been demonstrated in 0.25μm CMOS.

    Original languageEnglish
    Title of host publicationASICON 2005
    Subtitle of host publication2005 6th International Conference on ASIC, Proceedings
    Pages3-7
    Number of pages5
    Publication statusPublished - 2005 Dec 1
    EventASICON 2005: 2005 6th International Conference on ASIC - Shanghai, China
    Duration: 2005 Oct 242005 Oct 27

    Publication series

    NameASICON 2005: 2005 6th International Conference on ASIC, Proceedings
    Volume1

    Other

    OtherASICON 2005: 2005 6th International Conference on ASIC
    CountryChina
    CityShanghai
    Period05/10/2405/10/27

    ASJC Scopus subject areas

    • Engineering(all)

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  • Cite this

    Kuroda, T. (2005). Power reduction in high-speed inter-chip data communications. In ASICON 2005: 2005 6th International Conference on ASIC, Proceedings (pp. 3-7). [1611234] (ASICON 2005: 2005 6th International Conference on ASIC, Proceedings; Vol. 1).