Power reduction techniques for dynamically reconfigurable processor arrays

T. Nishimura, K. Hirai, Y. Saito, T. Nakamura, Y. Hasegawa, S. Tsutsusmi, V. Tunbunheng, H. Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfiguration power. Evaluation result shows that processing power for PEs is dominant and reconfiguration power is about 20.7% of the total dynamic power consumption. Based on the above evaluation results, we proposed two dynamic power reduction techniques: functional unit-level operand isolation and selective context fetch. Evaluation results demonstrate that the functional unit-level operand isolation can reduce up to 20.8% of the dynamic power with only 2.2% area overhead. On the selective context fetch, the power reduction is limited by the increasing of the additional hardware.

Original languageEnglish
Title of host publicationProceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
Pages305-310
Number of pages6
DOIs
Publication statusPublished - 2008 Nov 3
Event2008 International Conference on Field Programmable Logic and Applications, FPL - Heidelberg, Germany
Duration: 2008 Sep 82008 Sep 10

Publication series

NameProceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2008 International Conference on Field Programmable Logic and Applications, FPL
CountryGermany
CityHeidelberg
Period08/9/808/9/10

ASJC Scopus subject areas

  • Hardware and Architecture

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