Power reduction techniques for dynamically reconfigurable processor arrays

T. Nishimura, K. Hirai, Y. Saito, T. Nakamura, Y. Hasegawa, S. Tsutsusmi, V. Tunbunheng, H. Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

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Engineering & Materials Science