Practical methodology of post-layout gate sizing for 15% more power saving

Noriyuki Miura, Naoki Kato, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a practical methodology of post-layout gate sizing for power reduction. Wire capacitance presumed in logic synthesis typically contains excessive margin for better timing closure in layout design. Power waste due to this can be reduced by post-layout gate sizing based on information obtained by backannotation. In this paper, we discuss a theory of optimal gate sizing in a signal path with surplus timing. We also, propose a practical design methodology where standard cells are reselected from a cell library by the theory, replaced by engineering change order, and timing constraints are verified by a static timing analyzer. We have applied the methodology to a 700k-gate commercial application processor for 3G cellular phones. Even though the original design was optimized for 133MHz, 170mW operation in a 0.18μm CMOS technology, power dissipation was further squeezed by 15% in combinational logic without compromising the performance.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages434-437
Number of pages4
Publication statusPublished - 2004
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: 2004 Jan 272004 Jan 30

Other

OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
CountryJapan
CityYokohama
Period04/1/2704/1/30

Fingerprint

Energy dissipation
Capacitance
Wire
Logic Synthesis

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Miura, N., Kato, N., & Kuroda, T. (2004). Practical methodology of post-layout gate sizing for 15% more power saving. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 434-437)

Practical methodology of post-layout gate sizing for 15% more power saving. / Miura, Noriyuki; Kato, Naoki; Kuroda, Tadahiro.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 434-437.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Miura, N, Kato, N & Kuroda, T 2004, Practical methodology of post-layout gate sizing for 15% more power saving. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. pp. 434-437, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan, 04/1/27.
Miura N, Kato N, Kuroda T. Practical methodology of post-layout gate sizing for 15% more power saving. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 434-437
Miura, Noriyuki ; Kato, Naoki ; Kuroda, Tadahiro. / Practical methodology of post-layout gate sizing for 15% more power saving. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. pp. 434-437
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