Prediction router: Yet another low latency on-chip router architecture

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

59 Citations (Scopus)

Abstract

Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce the communication latency, we propose a lowlatency router architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration. In the prediction routers, incoming packets are transferred without waiting the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing the communication latency is the hit rates of prediction algorithms, which vary from the network environments, such asthe network topology, routing algorithm, and traffic pattern. Although typical low-latency routers that speculatively skip one or more pipeline stages use a bypass datapath for specific packet transfers (e.g., packets moving on the same dimension), our prediction router predictively forwards packets based on a prediction algorithm selected from several candidates in response to the network environments. In this paper, we analyze the prediction hit rates of six prediction algorithms on meshes, tori, and fat trees. Then we provide three case studies, each of which assumes different many-core architecture. We have implemented a prediction router for each case study by using a 65nm CMOS process, and evaluated them in terms of the prediction hit rate, zero load latency, hardware amount, and energy consumption. The results show that although the area and energy are increased by 6.4-15.9% and 8.0-9.5% respectively, up to 89.8% of the prediction hit rate is achieved in real applications, which provide favorable trade-offs between the modest hardware/energy overheads and the latency saving.

Original languageEnglish
Title of host publicationProceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009
Pages367-378
Number of pages12
DOIs
Publication statusPublished - 2009 Apr 24
Event2008 IEEE International Conference on Mechatronics and Automation, ICMA 2008 - Takamatsu, Japan
Duration: 2008 Aug 52008 Aug 8

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other2008 IEEE International Conference on Mechatronics and Automation, ICMA 2008
CountryJapan
CityTakamatsu
Period08/8/508/8/8

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ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Matsutani, H., Koibuchi, M., Amano, H., & Yoshinaga, T. (2009). Prediction router: Yet another low latency on-chip router architecture. In Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009 (pp. 367-378). [4798274] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2009.4798274