Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

Akihiro Shitara, Yuri Nishikawa, Masato Yoshimi, Takashi Abe, Toshimichi Ikemura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we introduce a GPU implementation and evaluation of batch learning self-organizing maps (BL-SOM) algorithm, which improves Kohonen's original SOM algorithm by making input data sequence independent from learning process. We used CUDA provided by NVIDIA Corporation for parallel programming, profiling, and data flow optimization so as to exploit inherent datalevel parallelism of the algorithm. With various parameter combinations, implementation on GTX280 achieved 250 times higher performance compared to Intel's Core2Quad Q6600 2.40GHz when parameters of map size, dimension of vectors, learning size and iteration of learning were 960×960, 136, 70 and 1, respectively.

Original languageEnglish
Title of host publicationProceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
Pages96-104
Number of pages9
Publication statusPublished - 2010 Jul 20
Event9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 - Innsbruck, Austria
Duration: 2010 Feb 162010 Feb 18

Publication series

NameProceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010

Other

Other9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010
CountryAustria
CityInnsbruck
Period10/2/1610/2/18

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Keywords

  • CUDA
  • GPGPU
  • GPU
  • Self-organizing map

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Software

Cite this

Shitara, A., Nishikawa, Y., Yoshimi, M., Abe, T., Ikemura, T., & Amano, H. (2010). Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor. In Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 (pp. 96-104). (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).