TY - GEN
T1 - Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface
AU - Tanabe, Noboru
AU - Kitamura, Akira
AU - Miyashiro, Tomotaka
AU - Miyabe, Yasuo
AU - Izawa, Tohru
AU - Hamada, Yoshihiro
AU - Nakajo, Hironori
AU - Amano, Hideharu
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2005
Y1 - 2005
N2 - Recent performance improvement of interconnection networks for a PC cluster brings a bottleneck in a standard I/O bus such as PCI bus. DIMMnet is a network interface plugged into a memory slot instead of standard I/O buses. This strategy is one of the solutions in order to balance growing performance with future micro processors. DIMMnet-2 is a prototype which can be plugged into a DDR-DIMM slot to confirm its functions. In this paper, outline of FPGA-based DIMMnet-2 prototype and improvements from DIMMnet-1 to DIMMnet-2 are mentioned. Although the DIMMnet-2 uses an FPGA instead of an ASIC, the latency for writing 8 Bytes into remote memory is only 0.948μs. It is about 3 times fewer latency than that of a high performance commercial network interface QsNET II plugged into PCI-X bus on Intel-based IA32 PC. The delay of CoreLogic part for BOTF sending of FPGA based DIMMnet-2 is 5.75 times as fast as that of DIMMnet-1.
AB - Recent performance improvement of interconnection networks for a PC cluster brings a bottleneck in a standard I/O bus such as PCI bus. DIMMnet is a network interface plugged into a memory slot instead of standard I/O buses. This strategy is one of the solutions in order to balance growing performance with future micro processors. DIMMnet-2 is a prototype which can be plugged into a DDR-DIMM slot to confirm its functions. In this paper, outline of FPGA-based DIMMnet-2 prototype and improvements from DIMMnet-1 to DIMMnet-2 are mentioned. Although the DIMMnet-2 uses an FPGA instead of an ASIC, the latency for writing 8 Bytes into remote memory is only 0.948μs. It is about 3 times fewer latency than that of a high performance commercial network interface QsNET II plugged into PCI-X bus on Intel-based IA32 PC. The delay of CoreLogic part for BOTF sending of FPGA based DIMMnet-2 is 5.75 times as fast as that of DIMMnet-1.
UR - http://www.scopus.com/inward/record.url?scp=33846980071&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33846980071&partnerID=8YFLogxK
U2 - 10.1109/IWIA.2005.38
DO - 10.1109/IWIA.2005.38
M3 - Conference contribution
AN - SCOPUS:33846980071
SN - 0769524834
SN - 9780769524832
T3 - Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
SP - 9
EP - 17
BT - IWIA 2005
PB - IEEE Computer Society
T2 - IWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems
Y2 - 17 January 2005 through 19 January 2005
ER -