Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface

Noboru Tanabe, Akira Kitamura, Tomotaka Miyashiro, Yasuo Miyabe, Tohru Izawa, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Recent performance improvement of interconnection networks for a PC cluster brings a bottleneck in a standard I/O bus such as PCI bus. DIMMnet is a network interface plugged into a memory slot instead of standard I/O buses. This strategy is one of the solutions in order to balance growing performance with future micro processors. DIMMnet-2 is a prototype which can be plugged into a DDR-DIMM slot to confirm its functions. In this paper, outline of FPGA-based DIMMnet-2 prototype and improvements from DIMMnet-1 to DIMMnet-2 are mentioned. Although the DIMMnet-2 uses an FPGA instead of an ASIC, the latency for writing 8 Bytes into remote memory is only 0.948μs. It is about 3 times fewer latency than that of a high performance commercial network interface QsNET II plugged into PCI-X bus on Intel-based IA32 PC. The delay of CoreLogic part for BOTF sending of FPGA based DIMMnet-2 is 5.75 times as fast as that of DIMMnet-1.

Original languageEnglish
Title of host publicationProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
Pages119-127
Number of pages9
Volume2005
DOIs
Publication statusPublished - 2005
EventIWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems - Oahu, HI, United States
Duration: 2005 Jan 172005 Jan 19

Other

OtherIWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems
CountryUnited States
CityOahu, HI
Period05/1/1705/1/19

Fingerprint

Interfaces (computer)
Field programmable gate arrays (FPGA)
Data storage equipment
Application specific integrated circuits

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Izawa, T., Hamada, Y., ... Amano, H. (2005). Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface. In Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems (Vol. 2005, pp. 119-127). [1587833] https://doi.org/10.1109/IWIA.2005.38

Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface. / Tanabe, Noboru; Kitamura, Akira; Miyashiro, Tomotaka; Miyabe, Yasuo; Izawa, Tohru; Hamada, Yoshihiro; Nakajo, Hironori; Amano, Hideharu.

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. Vol. 2005 2005. p. 119-127 1587833.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tanabe, N, Kitamura, A, Miyashiro, T, Miyabe, Y, Izawa, T, Hamada, Y, Nakajo, H & Amano, H 2005, Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface. in Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. vol. 2005, 1587833, pp. 119-127, IWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems, Oahu, HI, United States, 05/1/17. https://doi.org/10.1109/IWIA.2005.38
Tanabe N, Kitamura A, Miyashiro T, Miyabe Y, Izawa T, Hamada Y et al. Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface. In Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. Vol. 2005. 2005. p. 119-127. 1587833 https://doi.org/10.1109/IWIA.2005.38
Tanabe, Noboru ; Kitamura, Akira ; Miyashiro, Tomotaka ; Miyabe, Yasuo ; Izawa, Tohru ; Hamada, Yoshihiro ; Nakajo, Hironori ; Amano, Hideharu. / Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. Vol. 2005 2005. pp. 119-127
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