Abstract
This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.
| Original language | English |
|---|---|
| Pages | 178-183 |
| Number of pages | 6 |
| Publication status | Published - 1994 Dec 1 |
| Event | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA Duration: 1994 Oct 10 → 1994 Oct 12 |
Other
| Other | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors |
|---|---|
| City | Cambridge, MA, USA |
| Period | 94/10/10 → 94/10/12 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Fingerprint Dive into the research topics of 'PROTEUS: Programmable hardware for telecommunication systems'. Together they form a unique fingerprint.
Cite this
Ohta, N., Nakada, H., Yamada, K., Tsutsui, A., & Miyazaki, T. (1994). PROTEUS: Programmable hardware for telecommunication systems. 178-183. Paper presented at Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, .