Abstract
This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 178-183 |
| Number of pages | 6 |
| Publication status | Published - 1994 |
| Event | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA Duration: 1994 Oct 10 → 1994 Oct 12 |
Other
| Other | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors |
|---|---|
| City | Cambridge, MA, USA |
| Period | 94/10/10 → 94/10/12 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
PROTEUS : Programmable hardware for telecommunication systems. / Ohta, N.; Nakada, H.; Yamada, K.; Tsutsui, A.; Miyazaki, T.
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. IEEE, 1994. p. 178-183.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - PROTEUS
T2 - Programmable hardware for telecommunication systems
AU - Ohta, N.
AU - Nakada, H.
AU - Yamada, K.
AU - Tsutsui, A.
AU - Miyazaki, T.
PY - 1994
Y1 - 1994
N2 - This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.
AB - This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.
UR - http://www.scopus.com/inward/record.url?scp=0028757574&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0028757574&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0028757574
SP - 178
EP - 183
BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
A2 - Anon, null
PB - IEEE
ER -