Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction

Ryouya Tanaka, Takumi Deguchi, Nobuhiko Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose an automatic synchronous PLL system for N-path filter for hum noise reduction in EEG(electroencephalogram) measurement by 0.18 μm CMOS process. Monitored common mode waveform contains Hum noise frequency component during EEG measurement is used for a master clock frequency of the N-path filter. The hum noise frequency as a master clock of the PLL is compared with a rectangular wave obtained by dividing the output frequency of the VCO which is aimed to oscillate at 400 or 480 Hz by 8. The oscillation frequency of the VCO is controlled by the bias voltage. The output signal of the VCO is inputted to a logic circuit that generates an 8-bit digital waveform, and the output for controlling the N-path filter is generated. It is possible to attenuate 50 or 60 Hz component of the EEG signal contains hum noise through an N-path (N = 8) filter. We simulated the PLL (PFD-CP, VCO), logic circuit, N-path filter and measured characteristics of the implemented PLL and logic circuit in this research.

Original languageEnglish
Title of host publication2017 International Symposium on Electronics and Smart Devices, ISESD 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages295-299
Number of pages5
Volume2018-January
ISBN (Electronic)9781538627785
DOIs
Publication statusPublished - 2018 Jan 9
Event2nd International Symposium on Electronics and Smart Devices, ISESD 2017 - Yogyakarta, Indonesia
Duration: 2017 Oct 172017 Oct 19

Other

Other2nd International Symposium on Electronics and Smart Devices, ISESD 2017
CountryIndonesia
CityYogyakarta
Period17/10/1717/10/19

Fingerprint

Switched filters
hum
Noise Reduction
Variable frequency oscillators
Phase locked loops
Noise abatement
noise reduction
voltage controlled oscillators
Logic circuits
Electroencephalography
electroencephalography
logic circuits
prototypes
Prototype
Filter
filters
Path
Clocks
Logic
Waveform

ASJC Scopus subject areas

  • Instrumentation
  • Artificial Intelligence
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Control and Optimization

Cite this

Tanaka, R., Deguchi, T., & Nakano, N. (2018). Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction. In 2017 International Symposium on Electronics and Smart Devices, ISESD 2017 (Vol. 2018-January, pp. 295-299). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISESD.2017.8253352

Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction. / Tanaka, Ryouya; Deguchi, Takumi; Nakano, Nobuhiko.

2017 International Symposium on Electronics and Smart Devices, ISESD 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 295-299.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tanaka, R, Deguchi, T & Nakano, N 2018, Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction. in 2017 International Symposium on Electronics and Smart Devices, ISESD 2017. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 295-299, 2nd International Symposium on Electronics and Smart Devices, ISESD 2017, Yogyakarta, Indonesia, 17/10/17. https://doi.org/10.1109/ISESD.2017.8253352
Tanaka R, Deguchi T, Nakano N. Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction. In 2017 International Symposium on Electronics and Smart Devices, ISESD 2017. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 295-299 https://doi.org/10.1109/ISESD.2017.8253352
Tanaka, Ryouya ; Deguchi, Takumi ; Nakano, Nobuhiko. / Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction. 2017 International Symposium on Electronics and Smart Devices, ISESD 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 295-299
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