Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction

Ryouya Tanaka, Takumi Deguchi, Nobuhiko Nakano

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    We propose an automatic synchronous PLL system for N-path filter for hum noise reduction in EEG(electroencephalogram) measurement by 0.18 μm CMOS process. Monitored common mode waveform contains Hum noise frequency component during EEG measurement is used for a master clock frequency of the N-path filter. The hum noise frequency as a master clock of the PLL is compared with a rectangular wave obtained by dividing the output frequency of the VCO which is aimed to oscillate at 400 or 480 Hz by 8. The oscillation frequency of the VCO is controlled by the bias voltage. The output signal of the VCO is inputted to a logic circuit that generates an 8-bit digital waveform, and the output for controlling the N-path filter is generated. It is possible to attenuate 50 or 60 Hz component of the EEG signal contains hum noise through an N-path (N = 8) filter. We simulated the PLL (PFD-CP, VCO), logic circuit, N-path filter and measured characteristics of the implemented PLL and logic circuit in this research.

    Original languageEnglish
    Title of host publication2017 International Symposium on Electronics and Smart Devices, ISESD 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages295-299
    Number of pages5
    ISBN (Electronic)9781538627785
    DOIs
    Publication statusPublished - 2017 Jul 1
    Event2nd International Symposium on Electronics and Smart Devices, ISESD 2017 - Yogyakarta, Indonesia
    Duration: 2017 Oct 172017 Oct 19

    Publication series

    Name2017 International Symposium on Electronics and Smart Devices, ISESD 2017
    Volume2018-January

    Other

    Other2nd International Symposium on Electronics and Smart Devices, ISESD 2017
    CountryIndonesia
    CityYogyakarta
    Period17/10/1717/10/19

    ASJC Scopus subject areas

    • Instrumentation
    • Artificial Intelligence
    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Control and Optimization

    Fingerprint Dive into the research topics of 'Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction'. Together they form a unique fingerprint.

  • Cite this

    Tanaka, R., Deguchi, T., & Nakano, N. (2017). Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction. In 2017 International Symposium on Electronics and Smart Devices, ISESD 2017 (pp. 295-299). (2017 International Symposium on Electronics and Smart Devices, ISESD 2017; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISESD.2017.8253352