TY - GEN
T1 - Prototype and measurement of automatic synchronous PLL system for N-path filter for hum noise reduction
AU - Tanaka, Ryouya
AU - Deguchi, Takumi
AU - Nakano, Nobuhiko
PY - 2017/7/1
Y1 - 2017/7/1
N2 - We propose an automatic synchronous PLL system for N-path filter for hum noise reduction in EEG(electroencephalogram) measurement by 0.18 μm CMOS process. Monitored common mode waveform contains Hum noise frequency component during EEG measurement is used for a master clock frequency of the N-path filter. The hum noise frequency as a master clock of the PLL is compared with a rectangular wave obtained by dividing the output frequency of the VCO which is aimed to oscillate at 400 or 480 Hz by 8. The oscillation frequency of the VCO is controlled by the bias voltage. The output signal of the VCO is inputted to a logic circuit that generates an 8-bit digital waveform, and the output for controlling the N-path filter is generated. It is possible to attenuate 50 or 60 Hz component of the EEG signal contains hum noise through an N-path (N = 8) filter. We simulated the PLL (PFD-CP, VCO), logic circuit, N-path filter and measured characteristics of the implemented PLL and logic circuit in this research.
AB - We propose an automatic synchronous PLL system for N-path filter for hum noise reduction in EEG(electroencephalogram) measurement by 0.18 μm CMOS process. Monitored common mode waveform contains Hum noise frequency component during EEG measurement is used for a master clock frequency of the N-path filter. The hum noise frequency as a master clock of the PLL is compared with a rectangular wave obtained by dividing the output frequency of the VCO which is aimed to oscillate at 400 or 480 Hz by 8. The oscillation frequency of the VCO is controlled by the bias voltage. The output signal of the VCO is inputted to a logic circuit that generates an 8-bit digital waveform, and the output for controlling the N-path filter is generated. It is possible to attenuate 50 or 60 Hz component of the EEG signal contains hum noise through an N-path (N = 8) filter. We simulated the PLL (PFD-CP, VCO), logic circuit, N-path filter and measured characteristics of the implemented PLL and logic circuit in this research.
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U2 - 10.1109/ISESD.2017.8253352
DO - 10.1109/ISESD.2017.8253352
M3 - Conference contribution
AN - SCOPUS:85047526716
T3 - 2017 International Symposium on Electronics and Smart Devices, ISESD 2017
SP - 295
EP - 299
BT - 2017 International Symposium on Electronics and Smart Devices, ISESD 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd International Symposium on Electronics and Smart Devices, ISESD 2017
Y2 - 17 October 2017 through 19 October 2017
ER -