Proximity inter-chip communication

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm. CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.

Original languageEnglish
Title of host publicationICSICT-2006
Subtitle of host publication2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
PublisherIEEE Computer Society
Pages1841-1844
Number of pages4
ISBN (Print)1424401615, 9781424401611
DOIs
Publication statusPublished - 2006 Jan 1
EventICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: 2006 Oct 232006 Oct 26

Publication series

NameICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

OtherICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period06/10/2306/10/26

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kuroda, T. (2006). Proximity inter-chip communication. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 1841-1844). [4098558] (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). IEEE Computer Society. https://doi.org/10.1109/ICSICT.2006.306462