RAM-based hardware accelerator for network data anonymization

Fumito Yamaguchi; Kanae Matsui; Hiroaki Nishi

doi:10.1109/FPL.2014.6927400

RAM-based hardware accelerator for network data anonymization

Fumito Yamaguchi, Kanae Matsui, Hiroaki Nishi

Department of System Design Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.

Original language	English
Title of host publication	Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9783000446450
DOIs	https://doi.org/10.1109/FPL.2014.6927400
Publication status	Published - 2014 Oct 16
Event	24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany Duration: 2014 Sep 1 → 2014 Sep 5

Publication series

Name	Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

Other

Other	24th International Conference on Field Programmable Logic and Applications, FPL 2014
Country/Territory	Germany
City	Munich
Period	14/9/1 → 14/9/5

Keywords

Anonymization
Deep Packet Inspection
FPGA
k-anonymity
l-diversity

ASJC Scopus subject areas

Computer Science Applications
Hardware and Architecture

Access to Document

10.1109/FPL.2014.6927400

Cite this

Yamaguchi, F., Matsui, K., & Nishi, H. (2014). RAM-based hardware accelerator for network data anonymization. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 [6927400] (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2014.6927400

RAM-based hardware accelerator for network data anonymization. / Yamaguchi, Fumito; Matsui, Kanae; Nishi, Hiroaki.

Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6927400 (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yamaguchi, F, Matsui, K & Nishi, H 2014, RAM-based hardware accelerator for network data anonymization. in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014., 6927400, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Institute of Electrical and Electronics Engineers Inc., 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 14/9/1. https://doi.org/10.1109/FPL.2014.6927400

Yamaguchi F, Matsui K, Nishi H. RAM-based hardware accelerator for network data anonymization. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6927400. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014). https://doi.org/10.1109/FPL.2014.6927400

Yamaguchi, Fumito ; Matsui, Kanae ; Nishi, Hiroaki. / RAM-based hardware accelerator for network data anonymization. Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

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RAM-based hardware accelerator for network data anonymization

Abstract

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Keywords

ASJC Scopus subject areas

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