Abstract
Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.
| Original language | English |
|---|---|
| Title of host publication | Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Print) | 9783000446450 |
| DOIs | |
| Publication status | Published - 2014 Oct 16 |
| Event | 24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany Duration: 2014 Sep 1 → 2014 Sep 5 |
Other
| Other | 24th International Conference on Field Programmable Logic and Applications, FPL 2014 |
|---|---|
| Country | Germany |
| City | Munich |
| Period | 14/9/1 → 14/9/5 |
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Keywords
- Anonymization
- Deep Packet Inspection
- FPGA
- k-anonymity
- l-diversity
ASJC Scopus subject areas
- Computer Science Applications
- Hardware and Architecture
Cite this
RAM-based hardware accelerator for network data anonymization. / Yamaguchi, Fumito; Matsui, Kanae; Nishi, Hiroaki.
Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6927400.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - RAM-based hardware accelerator for network data anonymization
AU - Yamaguchi, Fumito
AU - Matsui, Kanae
AU - Nishi, Hiroaki
PY - 2014/10/16
Y1 - 2014/10/16
N2 - Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.
AB - Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.
KW - Anonymization
KW - Deep Packet Inspection
KW - FPGA
KW - k-anonymity
KW - l-diversity
UR - http://www.scopus.com/inward/record.url?scp=84911090936&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84911090936&partnerID=8YFLogxK
U2 - 10.1109/FPL.2014.6927400
DO - 10.1109/FPL.2014.6927400
M3 - Conference contribution
SN - 9783000446450
BT - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
PB - Institute of Electrical and Electronics Engineers Inc.
ER -