RAM-based hardware accelerator for network data anonymization

Fumito Yamaguchi, Kanae Matsui, Hiroaki Nishi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.

Original languageEnglish
Title of host publicationConference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9783000446450
DOIs
Publication statusPublished - 2014 Oct 16
Event24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany
Duration: 2014 Sep 12014 Sep 5

Other

Other24th International Conference on Field Programmable Logic and Applications, FPL 2014
CountryGermany
CityMunich
Period14/9/114/9/5

Fingerprint

Random access storage
Intrusion detection
Application programs
Particle accelerators
Inspection
Throughput
Hardware

Keywords

  • Anonymization
  • Deep Packet Inspection
  • FPGA
  • k-anonymity
  • l-diversity

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

Cite this

Yamaguchi, F., Matsui, K., & Nishi, H. (2014). RAM-based hardware accelerator for network data anonymization. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 [6927400] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2014.6927400

RAM-based hardware accelerator for network data anonymization. / Yamaguchi, Fumito; Matsui, Kanae; Nishi, Hiroaki.

Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6927400.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yamaguchi, F, Matsui, K & Nishi, H 2014, RAM-based hardware accelerator for network data anonymization. in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014., 6927400, Institute of Electrical and Electronics Engineers Inc., 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 14/9/1. https://doi.org/10.1109/FPL.2014.6927400
Yamaguchi F, Matsui K, Nishi H. RAM-based hardware accelerator for network data anonymization. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6927400 https://doi.org/10.1109/FPL.2014.6927400
Yamaguchi, Fumito ; Matsui, Kanae ; Nishi, Hiroaki. / RAM-based hardware accelerator for network data anonymization. Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014.
@inproceedings{247f1659ff1d4f22a153ead93413e372,
title = "RAM-based hardware accelerator for network data anonymization",
abstract = "Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.",
keywords = "Anonymization, Deep Packet Inspection, FPGA, k-anonymity, l-diversity",
author = "Fumito Yamaguchi and Kanae Matsui and Hiroaki Nishi",
year = "2014",
month = "10",
day = "16",
doi = "10.1109/FPL.2014.6927400",
language = "English",
isbn = "9783000446450",
booktitle = "Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - RAM-based hardware accelerator for network data anonymization

AU - Yamaguchi, Fumito

AU - Matsui, Kanae

AU - Nishi, Hiroaki

PY - 2014/10/16

Y1 - 2014/10/16

N2 - Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.

AB - Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.

KW - Anonymization

KW - Deep Packet Inspection

KW - FPGA

KW - k-anonymity

KW - l-diversity

UR - http://www.scopus.com/inward/record.url?scp=84911090936&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84911090936&partnerID=8YFLogxK

U2 - 10.1109/FPL.2014.6927400

DO - 10.1109/FPL.2014.6927400

M3 - Conference contribution

SN - 9783000446450

BT - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

PB - Institute of Electrical and Electronics Engineers Inc.

ER -