Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication

Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Three-dimensional stacked memory is considered to be one of the innovative elements for the next-generation computing system, for it provides high bandwidth and energy efficiency. Particularly, packet routing ability of Hybrid Memory Cubes (HMCs) enables new interconnects for the memories, giving flexibility to its topological design space. Since memory-processor communication is latency-sensitive, our challenge is to alleviate latency of the memory interconnection network, which is subject to high overheads from hop-count increase. Interestingly, random network topologies are known to have remarkably low diameter that is even comparable to theoretical Moore graph. In this context, we first propose to exploit the random topologies for the memory networks. Second, we also propose several optimizations to leverage the random topologies to be further adaptive to the latency-sensitive memory-processor communication: communication path length based selection, deterministic minimal routing, and page-size granularity memory mapping. Finally, we present interesting results of our evaluation: the random networks with universal memory access outperformed non-random networks of which memory access was optimally localized.

Original languageEnglish
Title of host publicationProceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages168-175
Number of pages8
ISBN (Print)9781467387750
DOIs
Publication statusPublished - 2016 Mar 31
Event24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016 - Heraklion, Crete, Greece
Duration: 2016 Feb 172016 Feb 19

Other

Other24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016
CountryGreece
CityHeraklion, Crete
Period16/2/1716/2/19

Fingerprint

Latency
Data storage equipment
Communication
Random Networks
Topology
Packet Routing
Interconnection Networks
Path Length
Interconnect
Granularity
Energy Efficiency
Leverage
Network Topology
Regular hexahedron
Energy efficiency
Count
Routing
Flexibility
Bandwidth
Three-dimensional

Keywords

  • 3D stacked memory
  • Memory network
  • Random topology

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software
  • Control and Optimization

Cite this

Fujiki, D., Matsutani, H., Koibuchi, M., & Amano, H. (2016). Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. In Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016 (pp. 168-175). [7445327] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PDP.2016.18

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. / Fujiki, Daichi; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 168-175 7445327.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fujiki, D, Matsutani, H, Koibuchi, M & Amano, H 2016, Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. in Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016., 7445327, Institute of Electrical and Electronics Engineers Inc., pp. 168-175, 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, Heraklion, Crete, Greece, 16/2/17. https://doi.org/10.1109/PDP.2016.18
Fujiki D, Matsutani H, Koibuchi M, Amano H. Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. In Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 168-175. 7445327 https://doi.org/10.1109/PDP.2016.18
Fujiki, Daichi ; Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu. / Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 168-175
@inproceedings{ee8f091c75024edc997151c0aea07588,
title = "Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication",
abstract = "Three-dimensional stacked memory is considered to be one of the innovative elements for the next-generation computing system, for it provides high bandwidth and energy efficiency. Particularly, packet routing ability of Hybrid Memory Cubes (HMCs) enables new interconnects for the memories, giving flexibility to its topological design space. Since memory-processor communication is latency-sensitive, our challenge is to alleviate latency of the memory interconnection network, which is subject to high overheads from hop-count increase. Interestingly, random network topologies are known to have remarkably low diameter that is even comparable to theoretical Moore graph. In this context, we first propose to exploit the random topologies for the memory networks. Second, we also propose several optimizations to leverage the random topologies to be further adaptive to the latency-sensitive memory-processor communication: communication path length based selection, deterministic minimal routing, and page-size granularity memory mapping. Finally, we present interesting results of our evaluation: the random networks with universal memory access outperformed non-random networks of which memory access was optimally localized.",
keywords = "3D stacked memory, Memory network, Random topology",
author = "Daichi Fujiki and Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano",
year = "2016",
month = "3",
day = "31",
doi = "10.1109/PDP.2016.18",
language = "English",
isbn = "9781467387750",
pages = "168--175",
booktitle = "Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication

AU - Fujiki, Daichi

AU - Matsutani, Hiroki

AU - Koibuchi, Michihiro

AU - Amano, Hideharu

PY - 2016/3/31

Y1 - 2016/3/31

N2 - Three-dimensional stacked memory is considered to be one of the innovative elements for the next-generation computing system, for it provides high bandwidth and energy efficiency. Particularly, packet routing ability of Hybrid Memory Cubes (HMCs) enables new interconnects for the memories, giving flexibility to its topological design space. Since memory-processor communication is latency-sensitive, our challenge is to alleviate latency of the memory interconnection network, which is subject to high overheads from hop-count increase. Interestingly, random network topologies are known to have remarkably low diameter that is even comparable to theoretical Moore graph. In this context, we first propose to exploit the random topologies for the memory networks. Second, we also propose several optimizations to leverage the random topologies to be further adaptive to the latency-sensitive memory-processor communication: communication path length based selection, deterministic minimal routing, and page-size granularity memory mapping. Finally, we present interesting results of our evaluation: the random networks with universal memory access outperformed non-random networks of which memory access was optimally localized.

AB - Three-dimensional stacked memory is considered to be one of the innovative elements for the next-generation computing system, for it provides high bandwidth and energy efficiency. Particularly, packet routing ability of Hybrid Memory Cubes (HMCs) enables new interconnects for the memories, giving flexibility to its topological design space. Since memory-processor communication is latency-sensitive, our challenge is to alleviate latency of the memory interconnection network, which is subject to high overheads from hop-count increase. Interestingly, random network topologies are known to have remarkably low diameter that is even comparable to theoretical Moore graph. In this context, we first propose to exploit the random topologies for the memory networks. Second, we also propose several optimizations to leverage the random topologies to be further adaptive to the latency-sensitive memory-processor communication: communication path length based selection, deterministic minimal routing, and page-size granularity memory mapping. Finally, we present interesting results of our evaluation: the random networks with universal memory access outperformed non-random networks of which memory access was optimally localized.

KW - 3D stacked memory

KW - Memory network

KW - Random topology

UR - http://www.scopus.com/inward/record.url?scp=84968911894&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84968911894&partnerID=8YFLogxK

U2 - 10.1109/PDP.2016.18

DO - 10.1109/PDP.2016.18

M3 - Conference contribution

AN - SCOPUS:84968911894

SN - 9781467387750

SP - 168

EP - 175

BT - Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -