Abstract
To implement reduced hierarchical bit-map directory (RHBD) scheme efficiently, a novel interconnection network Recursive Diagonal Torus (RDT) chip which equips hierarchical multicast mechanism without clock and acknowledge combining mechanism is developed. It transfers all packets synchronized with a unique central processing unit clock by using 0.5 μBiCMOS silicon on glass technology. It also allows packet users to push and pull a flit of the packet simultaneously. These mixed design approach with schematic and very high speed integrated circuit hardware description languages permits development of these complicated chips.
Original language | English |
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Pages | 675-676 |
Number of pages | 2 |
Publication status | Published - 1997 Jan 1 |
Event | Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn Duration: 1997 Jan 28 → 1997 Jan 31 |
Other
Other | Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC |
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City | Chiba, Jpn |
Period | 97/1/28 → 97/1/31 |
ASJC Scopus subject areas
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering