RDT network router chip

Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Ken ichiro Anjo, Tomohiro Kudoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To implement reduced hierarchical bit-map directory (RHBD) scheme efficiently, a novel interconnection network Recursive Diagonal Torus (RDT) chip which equips hierarchical multicast mechanism without clock and acknowledge combining mechanism is developed. It transfers all packets synchronized with a unique central processing unit clock by using 0.5 μBiCMOS silicon on glass technology. It also allows packet users to push and pull a flit of the packet simultaneously. These mixed design approach with schematic and very high speed integrated circuit hardware description languages permits development of these complicated chips.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
PublisherIEEE
Pages675-676
Number of pages2
Publication statusPublished - 1997
EventProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn
Duration: 1997 Jan 281997 Jan 31

Other

OtherProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
CityChiba, Jpn
Period97/1/2897/1/31

Fingerprint

Routers
Clocks
Computer hardware description languages
Schematic diagrams
Program processors
Integrated circuits
Glass
Silicon

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Nishi, H., Amano, H., Nishimura, K., Anjo, K. I., & Kudoh, T. (1997). RDT network router chip. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 675-676). IEEE.

RDT network router chip. / Nishi, Hiroaki; Amano, Hideharu; Nishimura, Katsunobu; Anjo, Ken ichiro; Kudoh, Tomohiro.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, 1997. p. 675-676.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nishi, H, Amano, H, Nishimura, K, Anjo, KI & Kudoh, T 1997, RDT network router chip. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, pp. 675-676, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, Chiba, Jpn, 97/1/28.
Nishi H, Amano H, Nishimura K, Anjo KI, Kudoh T. RDT network router chip. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE. 1997. p. 675-676
Nishi, Hiroaki ; Amano, Hideharu ; Nishimura, Katsunobu ; Anjo, Ken ichiro ; Kudoh, Tomohiro. / RDT network router chip. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, 1997. pp. 675-676
@inproceedings{57b3a3b7973b4c3398df8b818e1b416b,
title = "RDT network router chip",
abstract = "To implement reduced hierarchical bit-map directory (RHBD) scheme efficiently, a novel interconnection network Recursive Diagonal Torus (RDT) chip which equips hierarchical multicast mechanism without clock and acknowledge combining mechanism is developed. It transfers all packets synchronized with a unique central processing unit clock by using 0.5 μBiCMOS silicon on glass technology. It also allows packet users to push and pull a flit of the packet simultaneously. These mixed design approach with schematic and very high speed integrated circuit hardware description languages permits development of these complicated chips.",
author = "Hiroaki Nishi and Hideharu Amano and Katsunobu Nishimura and Anjo, {Ken ichiro} and Tomohiro Kudoh",
year = "1997",
language = "English",
pages = "675--676",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "IEEE",

}

TY - GEN

T1 - RDT network router chip

AU - Nishi, Hiroaki

AU - Amano, Hideharu

AU - Nishimura, Katsunobu

AU - Anjo, Ken ichiro

AU - Kudoh, Tomohiro

PY - 1997

Y1 - 1997

N2 - To implement reduced hierarchical bit-map directory (RHBD) scheme efficiently, a novel interconnection network Recursive Diagonal Torus (RDT) chip which equips hierarchical multicast mechanism without clock and acknowledge combining mechanism is developed. It transfers all packets synchronized with a unique central processing unit clock by using 0.5 μBiCMOS silicon on glass technology. It also allows packet users to push and pull a flit of the packet simultaneously. These mixed design approach with schematic and very high speed integrated circuit hardware description languages permits development of these complicated chips.

AB - To implement reduced hierarchical bit-map directory (RHBD) scheme efficiently, a novel interconnection network Recursive Diagonal Torus (RDT) chip which equips hierarchical multicast mechanism without clock and acknowledge combining mechanism is developed. It transfers all packets synchronized with a unique central processing unit clock by using 0.5 μBiCMOS silicon on glass technology. It also allows packet users to push and pull a flit of the packet simultaneously. These mixed design approach with schematic and very high speed integrated circuit hardware description languages permits development of these complicated chips.

UR - http://www.scopus.com/inward/record.url?scp=0030703006&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030703006&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0030703006

SP - 675

EP - 676

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

PB - IEEE

ER -