RDT network router chip

Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Ken ichiro Anjo, Tomohiro Kudoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To implement reduced hierarchical bit-map directory (RHBD) scheme efficiently, a novel interconnection network Recursive Diagonal Torus (RDT) chip which equips hierarchical multicast mechanism without clock and acknowledge combining mechanism is developed. It transfers all packets synchronized with a unique central processing unit clock by using 0.5 μBiCMOS silicon on glass technology. It also allows packet users to push and pull a flit of the packet simultaneously. These mixed design approach with schematic and very high speed integrated circuit hardware description languages permits development of these complicated chips.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
PublisherIEEE
Pages675-676
Number of pages2
Publication statusPublished - 1997
EventProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn
Duration: 1997 Jan 281997 Jan 31

Other

OtherProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
CityChiba, Jpn
Period97/1/2897/1/31

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Nishi, H., Amano, H., Nishimura, K., Anjo, K. I., & Kudoh, T. (1997). RDT network router chip. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 675-676). IEEE.