Real chip evaluation of a low power CGRA with optimized application mapping

Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng Anh Vu Doan, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Even though many optimization methods for CGRAs (Coarse-Grained Reconfigurable Architectures) have been proposed, aggressive power optimization still remains a complex problem to be solved. Moreover, the developments of these methods have mainly been proven on the basis of simulations. Therefore, the questions remains whether they can be applied for a real chip. Here, we consider a real implemented low power CGRA called CCSOTB2, and explore the possibility of the power reduction for this design. This paper proposes to use a metaheuristic method to optimize the power while considering all configurable factors of the CGRA, especially the mapping of an application. This methodology can generate mappings with their related pipeline structure and body bias control automatically. Optimized configurations to use on the real chip are obtained with this methodology and allow to measure the power consumption. The experimental results show a power reduction of 14.2% in average, when compared to a previously-used mapping method which cannot consider body bias and pipeline structure. In addition, the proposed method enables users to select a mapping from various solutions depending on performance requirement and trade-off possibilities (e.g. throughput vs power consumption).

Original languageEnglish
Title of host publicationProceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018
PublisherAssociation for Computing Machinery
ISBN (Electronic)9781450365420
DOIs
Publication statusPublished - 2018 Jun 20
Event9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018 - Toronto, Canada
Duration: 2018 Jun 202018 Jun 22

Other

Other9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018
CountryCanada
CityToronto
Period18/6/2018/6/22

ASJC Scopus subject areas

  • Human-Computer Interaction
  • Computer Networks and Communications
  • Computer Vision and Pattern Recognition
  • Software

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  • Cite this

    Kojima, T., Ando, N., Matshushita, Y., Okuhara, H., Doan, N. A. V., & Amano, H. (2018). Real chip evaluation of a low power CGRA with optimized application mapping. In Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018 [a13] Association for Computing Machinery. https://doi.org/10.1145/3241793.3241806