A new digital phase-locked loop (PLL) tested on a field programmable gate array (FPGA) was designed. Intrinsic synchronizability of electrical operators was utilized by PLL. Dynamically reconfigurable clock networks was provided by PLL which did not require an analog element like control voltage.
|Number of pages||2|
|Publication status||Published - 2001 Jan 18|
ASJC Scopus subject areas
- Electrical and Electronic Engineering