Reconfigurable phase-locked loops on FPGA utilizing intrinsic synchronizability

H. Tanaka, A. Hasegawa, S. Haruyama

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

A new digital phase-locked loop (PLL) tested on a field programmable gate array (FPGA) was designed. Intrinsic synchronizability of electrical operators was utilized by PLL. Dynamically reconfigurable clock networks was provided by PLL which did not require an analog element like control voltage.

Original languageEnglish
Pages (from-to)77-78
Number of pages2
JournalElectronics Letters
Volume37
Issue number2
DOIs
Publication statusPublished - 2001 Jan 18
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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