Reconfigurable systolic Viterbi decoder

Kazuya Takahashi, Hiroshi Tobita, Shinichiro Haruyama, Masao Nakagawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper introduces a new algorithm which saves the power consumption of the systolic Viterbi decoder. The new algorithm dynamically changes the trucated path length of a Viterbi decoder according to the channel condition, resulting in reduction of power consumption. This algorithm is based on the observation that the truncated path length and bit error rate are closely related. If we set the truncated path length short, we can reduce the size of the decoder even though the system performance is sacrificed. We propose reconfiguration of the truncated path length according to channel state. It is shown that power consumption of a systolic Viterbi decoder with convolutional code for a constraint length K = 3 and a code rate R = 1/2 can be eliminated over 20 percent at the bit error rate of 10-3 in a Rayleigh fading channel. Furthermore, the longer the truncated path length becomes, the more effective the proposed method is.

Original languageEnglish
Title of host publicationIEEE Vehicular Technology Conference
Pages1629-1632
Number of pages4
Volume50
Edition3
DOIs
Publication statusPublished - 1999
EventIEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall - Amsterdam, Netherlands
Duration: 1999 Sep 191999 Sep 22

Other

OtherIEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall
CountryNetherlands
CityAmsterdam
Period99/9/1999/9/22

Fingerprint

Path Length
Electric power utilization
Bit error rate
Power Consumption
Convolutional codes
Rayleigh fading
Error Rate
Fading channels
Convolutional Codes
Rayleigh Fading Channel
Reconfiguration
Percent
System Performance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Applied Mathematics

Cite this

Takahashi, K., Tobita, H., Haruyama, S., & Nakagawa, M. (1999). Reconfigurable systolic Viterbi decoder. In IEEE Vehicular Technology Conference (3 ed., Vol. 50, pp. 1629-1632). [801573] https://doi.org/10.1109/VETECF.1999.801573

Reconfigurable systolic Viterbi decoder. / Takahashi, Kazuya; Tobita, Hiroshi; Haruyama, Shinichiro; Nakagawa, Masao.

IEEE Vehicular Technology Conference. Vol. 50 3. ed. 1999. p. 1629-1632 801573.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takahashi, K, Tobita, H, Haruyama, S & Nakagawa, M 1999, Reconfigurable systolic Viterbi decoder. in IEEE Vehicular Technology Conference. 3 edn, vol. 50, 801573, pp. 1629-1632, IEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall, Amsterdam, Netherlands, 99/9/19. https://doi.org/10.1109/VETECF.1999.801573
Takahashi K, Tobita H, Haruyama S, Nakagawa M. Reconfigurable systolic Viterbi decoder. In IEEE Vehicular Technology Conference. 3 ed. Vol. 50. 1999. p. 1629-1632. 801573 https://doi.org/10.1109/VETECF.1999.801573
Takahashi, Kazuya ; Tobita, Hiroshi ; Haruyama, Shinichiro ; Nakagawa, Masao. / Reconfigurable systolic Viterbi decoder. IEEE Vehicular Technology Conference. Vol. 50 3. ed. 1999. pp. 1629-1632
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