Reducing instruction TLB's leakage power consumption for embedded processors

Zhao Lei, Hui Xu, Dasuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a leakage efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage structure which stores the recent address-translation information, the TLB access frequency can be drastically decreased and the instruction TLB can be turned into the low leakage mode with the dual voltage supply technique. Based on such a design philosophy, three different implementation policies are proposed. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01 % performance degradation.

Original languageEnglish
Title of host publication2010 International Conference on Green Computing, Green Comp 2010
PublisherIEEE Computer Society
Pages477-484
Number of pages8
ISBN (Print)9781424476138
DOIs
Publication statusPublished - 2010

Publication series

Name2010 International Conference on Green Computing, Green Comp 2010

Keywords

  • Embedded processor
  • Instruction TLB
  • Leakage power

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications

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