Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

Masayuki Kimura; Kazuei Hironaka; Hideharu Amano

doi:10.1109/FPT.2011.6132707

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

Masayuki Kimura, Kazuei Hironaka, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A power-consumption-centric assignment algorithm called partially fixed configuration mapping (PFCM) is proposed for multi-context dynamically reconfigurable processors. By assigning the same operations into the same PE (processing element) as many as possible, the amount of changing configuration data for dynamic reconfiguration can be reduced, resulting in the redundant power consumed for changing the configuration also being reduced. The proposed algorithm was implemented in a compiler for a dynamically reconfigurable processor for research. Evaluation results showed that the consumed power was reduced by 10% on average without increasing the execution time.

Original language	English
Title of host publication	2011 International Conference on Field-Programmable Technology, FPT 2011
DOIs	https://doi.org/10.1109/FPT.2011.6132707
Publication status	Published - 2011 Dec 1
Event	2011 International Conference on Field-Programmable Technology, FPT 2011 - New Delhi, India Duration: 2011 Dec 12 → 2011 Dec 14

Publication series

Name	2011 International Conference on Field-Programmable Technology, FPT 2011

Other

Other	2011 International Conference on Field-Programmable Technology, FPT 2011
Country/Territory	India
City	New Delhi
Period	11/12/12 → 11/12/14

ASJC Scopus subject areas

Computational Mathematics

Access to Document

10.1109/FPT.2011.6132707

Cite this

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. / Kimura, Masayuki; Hironaka, Kazuei; Amano, Hideharu.
2011 International Conference on Field-Programmable Technology, FPT 2011. 2011. 6132707 (2011 International Conference on Field-Programmable Technology, FPT 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kimura, M, Hironaka, K & Amano, H 2011, Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. in 2011 International Conference on Field-Programmable Technology, FPT 2011., 6132707, 2011 International Conference on Field-Programmable Technology, FPT 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, 11/12/12. https://doi.org/10.1109/FPT.2011.6132707

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Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

Abstract

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ASJC Scopus subject areas

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